The formats of some of the remaining operate instructions are shown below:

These instructions are available as illustrated in Normal Mode only. The instructions are also available in Local Mode and Simple Mode, but with modified opcodes. A subset of these instructions, in some cases lacking certain features, most commonly indexing, is available in Compact Mode.

The opcodes of these operate instructions, shown for convenience in all three modes, are as follows:

Normal Mode Simple Mode Local Mode Compact Mode ------------- ------------- ------------- --------------- 160xxx xxxxx0 000xxx xxxxx0 040xxx xxxxx0 0606xx xxxxx0 JMS Jump to Subroutine 162xxx xxxxx1 002xxx xxxxx0 042xxx xxxxx0 LMU Load Multiple 163xxx xxxxx1 003xxx xxxxx0 043xxx xxxxx0 STMU Store Multiple 164xxx xxxxx1 004xxx xxxxx0 044xxx xxxxx0 LMUBR Load Multiple Base Registers 165xxx xxxxx1 005xxx xxxxx0 045xxx xxxxx0 STMUBR Store Multiple Base Registers 166xxx xxxxx1 006xxx xxxxx0 046xxx xxxxx0 LMUQ Load Multiple Quad 167xxx xxxxx1 007xxx xxxxx0 047xxx xxxxx0 STMUQ Store Multiple Quad 1701x0 0101x0 0501x0 LBL Long Branch if Low 1702x0 0102x0 0502x0 LBE Long Branch if Equal 1703x0 0103x0 0503x0 LBLE Long Branch if Low or Equal 1704x0 0104x0 0504x0 LBH Long Branch if High 1705x0 0105x0 0505x0 LBNE Long Branch if Not Equal 1706x0 0106x0 0506x0 LBHE Long Branch if High or Equal 1707x0 0107x0 0507x0 LBNV Long Branch if No Overflow 1710x0 0110x0 0510x0 LBV Long Branch if Overflow 1712x0 0112x0 0512x0 LBC Long Branch if Carry 1713x0 0113x0 0513x0 LBNC Long Branch if No Carry 1717x0 0117x0 0517x0 LBRA Long Branch 172xx0 012xx0 052xx0 06x7x0 LBXH Long Branch if Index High 173xx0 013xx0 053xx0 07x7x0 LBXLE Long Branch if Index Low or Equal 174xx0 014xx0 054xx0 0707x0 LBRS Long Branch to Subroutine 1701xx xxxxx0 0101xx xxxxx0 0501xx xxxxx0 0617xx xxxxx0 JL Jump if Low 1702xx xxxxx0 0102xx xxxxx0 0502xx xxxxx0 0627xx xxxxx0 JE Jump if Equal 1703xx xxxxx0 0103xx xxxxx0 0503xx xxxxx0 0637xx xxxxx0 JLE Jump if Low or Equal 1704xx xxxxx0 0104xx xxxxx0 0504xx xxxxx0 0647xx xxxxx0 JH Jump if High 1705xx xxxxx0 0105xx xxxxx0 0505xx xxxxx0 0657xx xxxxx0 JNE Jump if Not Equal 1706xx xxxxx0 0106xx xxxxx0 0506xx xxxxx0 0667xx xxxxx0 JHE Jump if High or Equal 1707xx xxxxx0 0107xx xxxxx0 0507xx xxxxx0 0677xx xxxxx0 JNV Jump if No Overflow 1710xx xxxxx0 0110xx xxxxx0 0510xx xxxxx0 0707xx xxxxx0 JV Jump if Overflow 1712xx xxxxx0 0112xx xxxxx0 0512xx xxxxx0 0727xx xxxxx0 JC Jump if Carry 1713xx xxxxx0 0113xx xxxxx0 0513xx xxxxx0 0737xx xxxxx0 JNC Jump if No Carry 1717xx xxxxx0 0117xx xxxxx0 0517xx xxxxx0 0777xx xxxxx0 JMP Jump 1701xx xxxxx1 0101xx xxxxx1 0501xx xxxxx1 0617xx xxxxx1 JVL Jump if Saved Low 1702xx xxxxx1 0102xx xxxxx1 0502xx xxxxx1 0627xx xxxxx1 JVE Jump if Saved Equal 1703xx xxxxx1 0103xx xxxxx1 0503xx xxxxx1 0637xx xxxxx1 JVLE Jump if Saved Low or Equal 1704xx xxxxx1 0104xx xxxxx1 0504xx xxxxx1 0647xx xxxxx1 JVH Jump if Saved High 1705xx xxxxx1 0105xx xxxxx1 0505xx xxxxx1 0657xx xxxxx1 JVNE Jump if Saved Not Equal 1706xx xxxxx1 0106xx xxxxx1 0506xx xxxxx1 0667xx xxxxx1 JVHE Jump if Saved High or Equal 1707xx xxxxx1 0107xx xxxxx1 0507xx xxxxx1 0677xx xxxxx1 JVNV Jump if Saved No Overflow 1710xx xxxxx1 0110xx xxxxx1 0510xx xxxxx1 0707xx xxxxx1 JVV Jump if Saved Overflow 1712xx xxxxx1 0112xx xxxxx1 0512xx xxxxx1 0727xx xxxxx1 JVC Jump if Saved Carry 1713xx xxxxx1 0113xx xxxxx1 0513xx xxxxx1 0737xx xxxxx1 JVNC Jump if Saved No Carry 172xxx xxxxx0 012xxx xxxxx0 052xxx xxxxx0 JXH Jump if Index High 173xxx xxxxx0 013xxx xxxxx0 053xxx xxxxx0 JXLE Jump if Index Low or Equal 1720xx xxxxx1 0120xx xxxxx1 0520xx xxxxx1 SLBR Supplementary Load Base Register 1721xx xxxxx1 0121xx xxxxx1 0521xx xxxxx1 SSTBR Supplementary Store Base Register 1722xx xxxxx1 0122xx xxxxx1 0522xx xxxxx1 SLSB Supplementary Load Scratchpad Base 1723xx xxxxx1 0123xx xxxxx1 0523xx xxxxx1 SSSB Supplementary Store Scratchpad Base 1724xx xxxxx1 0124xx xxxxx1 0524xx xxxxx1 SLPSB Supplementary Load Pointer Scratchpad Base 1725xx xxxxx1 0125xx xxxxx1 0525xx xxxxx1 SSPSB Supplementary Store Pointer Scratchpad Base 1726xx xxxxx1 0126xx xxxxx1 0526xx xxxxx1 SLASB Supplementary Load Array Scratchpad Base 1727xx xxxxx1 0127xx xxxxx1 0527xx xxxxx1 SSASB Supplementary Store Array Scratchpad Base

The LM and STM instructions operate on a range of destination registers specified in the instruction, and are useful for saving and restoring registers when a subroutine is called. The LMBR and STMBR instructions, and the LMQ and STMQ instructions perform the same function for the base registers and the floating-point registers.

If the base register zero is indicated in these instructions, the address field is omitted. Unlike the case of standard memory-reference instructions, base register zero is used, however: in the case of a store instruction, it serves as a pointer to the memory to which information is stored, and the length of the information stored is then added to its contents; in the case of a load instruction, the length of the information to be read is first subtracted from its contents, and then it is used as a pointer to that information.

In other words, the load and store multiple instructions, when base register zero is indicated, are POP and PUSH instructions, with base register zero serving as a stack pointer.

The various supplementary load and store instructions provide memory-reference instructions which only have the simple register-memory addressing mode, to allow access to individual base and scratchpad registers.

Note that these instructions will execute successfully even when they are performing partly unaligned reading or writing of data, as the instruction format only enforces alignment to 32-bit boundaries. Also note that only the complete contents of a register may be placed on a stack or removed from it; there are no byte, halfword, floating or double PUSH or POP instructions.

These are the instructions which carry out a transfer of control, causing the steps of the program being executed to be fetched from an address different from the next one in sequence. Some of these instructions involve bits of the status word. There is a carry bit which is set, either to 0 or to 1, by operations that could produce a carry out of one of the 32-bit arithmetic/index registers. Also, other bits indicate if the result of an arithmetic operation, whether integer or floating-point, is positive, negative, or zero. These determine if a conditional jump instruction results in a jump.

The rR field in a JMS instruction refers to a base register rather than an arithmetic/index register. Thus, to return from a subroutine called by a JMS instruction, a jump instruction using the same base register and with an address field containing zero is used. (Note that a nonzero address field can be used if space following the JMS instruction is to be skipped because it is used to pass information, such as a pointer to an argument list, to the subroutine, following some manner of calling convention. Usually, however, the pointer to the argument list will be put in a register designated by convention for this purpose, such as base register 1.)

If the rR field is zero, however, instead of the return address being stored in base register zero, it is stored in the memory location pointed to by base register zero, which is then incremented by either 4 or 8. This allows the use of base register zero as a stack pointer, and the use of that stack for subroutine jumps.

The JV instruction transfers control if an overflow condition is present; the other conditional jumps never transfer control if an overflow is present.

If indexed addressing is used in a jump instruction, the instruction does not jump to the memory location at the effective address, but instead to the location whose address it contains. This addressing mode, post-indexed indirect addressing, allows branching to one of several locations in a list. This also applies to the JMS instruction.

As well, there is a second set of conditional jump instructions which operate from the alternate copy of condition codes which can be set by register-to-register instructions in Normal Mode, or by any instructions if the postfix supplementary bit is used to specify saving the condition code. This is intended to avoid the need for speculative execution and yet allow instructions to execute one after another at full speed on a pipelined implementation.

The JXH and JXLH instructions decrement and increment, respectively, the count register specified in the cR field, compare it to the limit register specified in the lR field, and jump if the count register is high in the first case, or low or equal in the second.

There are also Long Branch instructions, which correspond to the Jump instructions. For these instructions, the address field is replaced by a signed 16-bit quantity which indicates a number of halfwords from the address immediately following the instruction.

These instructions are indicated by a base register field of zero. Since the displacement occupies the entire 16-bit field, rather than being a halfword-aligned address, note that what would be multiple-register instructions as well as jump and loop instructions become long branch instructions when their base register fields contain zero.

The Extensible Shift instructions perform what is termed a "funnel shift", to facilitate shifting of multi-word operands of arbitrary length. The two instructions are:

160xx0 0xxxx0 ESL Extensible Shift Left 161xx0 0xxxx0 ESR Extensible Shift Right

The source argument consists of one arithmetic/index
register, and the destination
argument consists of two consecutive arithmetic/index
registers, and is *not* restricted to starting with an
even-numbered register.

In an Extensible Shift Left instruction, the source argument value is considered to initially occupy the rightmost portion of a space the size of the destination argument prior to being shifted left.

Similarly, in an Extensible Shift Right instruction, the source argument value is considered to initially occupy the leftmost portion of a space the size of the destination argument prior to being shifted right.

Note that it is always possible to perform the operation of one of these instructions with the other one, as only those shifts are valid which result in the source operand remaining entirely within the double-width field. However, both are retained for lower-performance implementations in which a shift operation may take a time proportional to the number of shifts specified.

Once the source argument value is prepared, then the destination is altered as follows:

Bits in the destination argument which do not correspond to bits from the original source argument are unchanged.

Bits in the destination argument which do correspond to a bit from the original source argument are replaced by one of the four bits in the four-bit connective field in the instruction, where these bits correspond, in order, to the possible combinations of a value for the source bit and the destination bit as follows:

Source bit: 0 0 1 1 Destination bit: 0 1 0 1

Thus, if the connective field contains 0111, those bits are replaced by the OR of the source bit and the destination bit; if the connective field contains 0011, the bits in the destination operand that correspond to bits in the original source operand are simply replaced by those bits. Note that a field of this type was used on the AN/FSQ-32 computer, but for general logical operations instead of only for this particular specialized logical operation.

The operate instructions in this group which are 16 bits in length have been seen in the chart for memory-reference instructions; their forms are:

The branch and floating single-operand instructions ara available only in Normal Mode. The other instructions, having opcodes in the range 020000-037777, are available in Normal Mode, Compressed Mode, and Simple Mode.

The opcodes of the shift instructions are:

030x6x SHLB Shift Left Byte 031x6x SHRB Shift Right Byte 033x6x ASRB Arithmetic Shift Right Byte 034x6x ROLB Rotate Left Byte 035x6x RORB Rotate Right Byte 036x6x RLCB Rotate Left through Carry Byte 037x6x RRCB Rotate Right through Carry Byte 030x4x SHLH Shift Left Halfword 031x4x SHRH Shift Right Halfword 033x4x ASRH Arithmetic Shift Right Halfword 034x4x ROLH Rotate Left Halfword 035x4x RORH Rotate Right Halfword 036x4x RLCH Rotate Left through Carry Halfword 037x4x RRCH Rotate Right through Carry Halfword 030x0x SHL Shift Left 031x0x SHR Shift Right 033x0x ASR Arithmetic Shift Right 034x0x ROL Rotate Left 035x0x ROR Rotate Right 036x0x RLC Rotate Left through Carry 037x0x RRC Rotate Right through Carry 020xxx SHLL Shift Left Long 021xxx SHRL Shift Right Long 023xxx ASRL Arithmetic Shift Right Long 024xxx ROLL Rotate Left Long 025xxx RORL Rotate Right Long 026xxx RLCL Rotate Left through Carry Long 027xxx RRCL Rotate Right through Carry Long

The opcodes of the branch instructions are:

101xx0 BL Branch if Low 102xx0 BE Branch if Equal 103xx0 BLE Branch if Low or Equal 104xx0 BH Branch if High 105xx0 BNE Branch if Not Equal 106xx0 BHE Branch if High or Equal 107xx0 BNV Branch if No Overflow 110xx0 BV Branch if Overflow 112xx0 BC Branch if Carry 113xx0 BNC Branch if No Carry 117xx0 BRA Branch

The opcodes of the return instructions are:

101000 RL Return if Low 102000 RE Return if Equal 103000 RLE Return if Low or Equal 104000 RH Return if High 105000 RNE Return if Not Equal 106000 RHE Return if High or Equal 107000 RNV Return if No Overflow 110000 RV Return if Overflow 112000 RC Return if Carry 113000 RNC Return if No Carry 117000 RSS Return from Stack Subroutine

When the displacement field of a branch instruction is zero, as this value would normally indicate the address of the instruction normally following the branch, instead of the instruction being a no-operation instruction, the opcode is used to indicate a conditional or unconditional return from a subroutine called by a jump to subroutine instruction with base register zero used as a stack pointer.

Note that this means branch instructions cannot safely have their displacements modified for some forms of self-modifying code (which is, in any case, inadvisable on a pipelined machine, and normally unneccessary when index registers are present, as well as being generally deprecated).

Thus, when the condition for a subroutine return is met, first base register zero is decremented by 4 or by 8, depending on whether 32-bit or 64-bit addressing is in use, and then the value at the address now contained in base register zero is used as the new value of the program counter.

A number of very basic operations, other than the shift instruction, which apply to a single operand are useful to have in a computer, such as complementing a value or clearing it to zero.

Several such operations are defined:

02220x CLR Clear 02230x CLRL Clear Long 02221x ABS Absolute Value 02231x ABSL Absolute Value Long 02222x INV Invert 02232x INVL Invert Long 02223x NEG Negate 02233x NEGL Negate Long

The Clear instruction sets a register to zero; the Invert instruction inverts all the bits; the Negate instruction produces the two's complement of the register's contents, producing no change in the register's value, and an overflow condition, if the register has its first bit set and all remaining bits zero. The Absolute Value instruction performs a Negate operation only if the register contents are negative.

The instructions

0224xx NB Normalize Byte 0225xx NH Normalize Halfword 0226xx N Normalize 0227xx NL Normalize Long

shift the contents of the source register left as many times as necessary to make the first bit of the source operand a 1, and store the number of required shifts in the destination register. The type of the instruction applies to the source operand: the destination always is a full 32-bit register.

As the instruction set described here is quite an elaborate one, designed to accelerate computations as much as possible, it is not unreasonable to include, as some existing architectures have already included, instructions to calculate various mathematical functions in hardware.

1200x0 SINM 1240x0 SIN 1300x0 SIND 1340x0 SINQ 1201x0 COSM 1241x0 COS 1301x0 COSD 1341x0 COSQ 1202x0 TANM 1242x0 TAN 1302x0 TAND 1342x0 TANQ 1204x0 ASNM 1244x0 ASN 1304x0 ASND 1344x0 ASNQ 1205x0 ACSM 1245x0 ACS 1305x0 ACSD 1345x0 ACSQ 1206x0 ATNM 1246x0 ATN 1306x0 ATND 1346x0 ATNQ 1210x0 SINHM 1250x0 SINH 1310x0 SINHD 1350x0 SINHQ 1211x0 COSHM 1251x0 COSH 1311x0 COSHD 1351x0 COSHQ 1212x0 TANHM 1252x0 TANH 1312x0 TANHD 1352x0 TANHQ 1214x0 ASNHM 1254x0 ASNH 1314x0 ASNHD 1354x0 ASNHQ 1215x0 ACSHM 1255x0 ACSH 1315x0 ACSHD 1355x0 ACSHQ 1216x0 ATNHM 1256x0 ATNH 1316x0 ATNHD 1356x0 ATNHQ 1220x0 SQRM 1260x0 SQR 1320x0 SQRD 1360x0 SQRQ 1221x0 QBRM 1261x0 QBR 1321x0 QBRD 1361x0 QBRQ 1222x0 LOGM 1262x0 LOG 1322x0 LOGD 1362x0 LOGQ 1223x0 EXPM 1263x0 EXP 1323x0 EXPD 1363x0 EXPQ 1364x0 CLRQ 1365x0 ABSQ 1366x0 SGNQ 1367x0 NEGQ

The LOG and EXP instructions operate to the base two; the hyperbolic functions are similarly scaled; the trignometric functions take their arguments in circles where one circle equals 360 degrees or two times pi radians, and the accuracy of the sine is limited for small arguments; the functions may be implemented by means of the CORDIC algorithm or related algorithms.

The SGNQ instruction produces 0 if its argument is zero, and +1 for a positive argument and -1 for a negative argument.