This section is concerned with the instructions having opcodes which begin with 140700.
Note that these instructions are available from Normal Mode (and Scratchpad Mode) only, as they belong to opcode space left available by what would be unaligned load/store instructions, except that they would have operated on bytes, to which such an operation is not applicable.
One group of instructions of this type, those which modify the Global Memory Map, will be discussed in the next section.
Having the same basic format as the load and store instructions, the input-output instructions deal with a separate address space to which no caching is applied. Of course, memory-mapped I/O and DMA are used for many input-output functions, but straightforwards input/output instructions are still useful to control or initiate DMA or other high-speed transfers.
140700 042xxx IN Input 140700 043xxx OUT Output
The eight 64-bit system registers can be accessed using instructions patterned after the multiple-register load and store instructions:
140700 152xxx LMSRR Load Multiple System Register Relative 140700 153xxx STMSRR Store Multiple System Register Relative 140700 154xxx LMSR Load Multiple System Register 140700 155xxx STMSR Store Multiple System Register 140700 156xxx LMSRSRR Load Multiple System Register System Register Relative 140700 157xxx STMSRSRR Store Multiple System Register System Register Relative
These instructions provide multiple register loads and stores for both the arithmetic-index registers and the system registers using the system registers instead of the base registers (LMSRR, STMSRR, LMSRSRR, STMSRSRR), and multiple register loads and stores for the system registers using the base registers (LMSR, STMSR).
For returning from an interrupt, the following instruction is provided:
140700 102xxx RFI Return From Interrupt
This memory-reference instruction accesses an operand which is 1,024 bits in length. The first 512 bits are loaded into the Program Status Block. The next 384 bits contain internal information in a possibly model-dependent format to permit a long instruction, interrupted during its performance, to be resumed after an interrupt. The final 128 bits contain 64-bit values to be placed in the two program counters.
Some necessary privileged instructions are highly model-dependent. An instruction will usually be needed to define, for a given Process ID, which portion, if any, of the on-chip register storage is used for each group of registers for that process.
It is possible, though, that an implementation might have a fixed allocation of register space to processes, and only permit process IDs 0 through 63 to be used. In such a case, instead of having a single continuous bank of register memory, each type of register would belong to its own space, and the allocation might be like this:
Process ID 0 - 1 Long Vector Scratchpad 0 - 1,
Long Vector Register Bank 0 - 1
Process ID 0 - 3 Supplementary Register Bank 0 - 3,
Explicit Bit-Matrix Multiply Register Bank 0 - 3
Process ID 0 - 31 Short Vector Register Bank 0 - 31
Base and Scratchpad Register Bank 0 - 31
Process ID 0 - 63 Floating Point Register Bank 0 - 63
Arithmetic-Index Register Bank 0 - 63
Process ID 32 - 63 Base Register Bank 0 - 31
where base registers can either be drawn from a bank of storage supplying a set of base registers only, or a bank of storage supplying a set of base registers together with a set of each of the three types of scratchpad registers.