The seven bit opcodes of the 16-bit register-to-register instructions and the memory-reference instructions in modes 00 and 01 follow the same basic pattern as used with the original CISC Concertina architecture and elsewhere:
0000 0001 0010 0011 0100 0101 0110 0111 SWB IB SWH IH SW I SWL 000 001 LB ULB LH ULH L UL LL 010 STB XB STH XH ST X STL XL 011 AB NB AH NH A N AL NL 100 SB OB SH OH S O SL OL 101 MH MEH M ME ML MEL 110 DH DEH D DE DL DEL 111 1000 1001 1010 1011 SWM SWF SWD SWQ 000 001 LM LF LD LQ 010 STM STF STD STQ 011 AM AF AD AQ 100 SM SF SD SQ 101 MM MF MD MQ 110 DM DF DD DQ 111
applying the types:
Fixed-point: B Byte 8 bits H Halfword 16 bits Integer 32 bits L Long 64 bits Floating-point: M Medium 48 bits (16-bit aligned) F Floating 32 bits D Double 64 bits Q Quad 128 bits
to the operations:
SW Swap L Load ST Store A Add S Subtract M Multiply D Divide I Insert UL Unsigned Load X Exclusive OR N AND O OR ME Multiply Extensibly DE Divide Extensibly
As on the System/360, Load performs sign extension of fixed-point quantities. Insert instead loads the operand into the least significant part of the destination register without changing the most significant part, and Unsigned Load clears the most significant part.
Multiply Extensibly produces a product that is twice the length of its terms.
Divide Extensibly involves a dividend that is twice the length of the divisor; both the quotient and the remainder are also twice as long as the divisor. Except for Divide Extensibly Long, the remainder is in the destination register, and the quotient is placed in the following register; in the case of Divide Extensibly Long, as the divisor is a 64 bit integer, the dividend, remainder, and quotient are all contained in register pairs.
The sixth through ninth lines of the first column show the shift instructions.
The available instructions are:
1100000 SLL Shift Left Long 1100001 LSRL Logical Shift Right Long 1100010 RLL Rotate Left Long 1100011 ASRL Arithmetic Shift Right Long 1100100...0nnnnn SL Shift Left 1100101...0nnnnn LSR Logical Shift Right 1100110...0nnnnn RL Rotate Left 1100111...0nnnnn ASR Arithmetic Shift Right 1100100...10nnnn SLH Shift Left Halfword 1100101...10nnnn LSRH Logical Shift Right Halfword 1100110...10nnnn RLH Rotate Left Halfword 1100111...10nnnn ASRH Arithmetic Shift Right Halfword 1100100...110nnn SLB Shift Left Byte 1100101...110nnn LSRB Logical Shift Right Byte 1100110...110nnn RLB Rotate Left Byte 1100111...110nnn ASRB Arithmetic Shift Right Byte
Due to a lack of opcode space, separate Arithmetic Shift Left and Logical Shift Left instructions are not provided in 16-bit form. In the first half of the instruction word, shift intructions cannot set the condition code, and there this distinction would be irrelevant.
The tenth line of the first column shows the 16-bit conditional branch instructions. These use an eight-bit relative displacement. This displacement is in units of 32 bits since instructions are considered to be normally aligned on 32-bit boundaries even though a 32-bit instruction word can sometimes be split into two 16-bit parts. Displacements are reckoned from the address of the 32-bit instruction word immediately following the conditional branch instruction itself.
Thus, a conditional branch in the first half of an instruction word with a displacement of zero is not a no-operation code, because it will still skip the short instruction in the second 16-bit half of the instruction word containing that branch.
The available instructions are:
151dd BLT Branch if Less Than 152dd BEQ Branch if Equal 153dd BLE Branch if Less than or Equal 154dd BGT Branch if Greater Than 155dd BNE Branch if Not Equal 156dd BGE Branch if Greater than or Equal 157dd BRA Branch 158dd BV Branch if oVerflow 159dd BNV Branch if No oVerflow 15Add BC Branch if Carry 15Bdd BNC Branch if No Carry
The fourth line shows the format of the set of conditional branch instructions placed within the opcode space for basic memory-reference instructions:
00601b JLT Jump if Less Than 00602b JEQ Jump if Equal 00603b JLE Jump if Less than or Equal 00604b JGT Jump if Greater Than 00605b JNE Jump if Not Equal 00606b JGE Jump if Greater than or Equal 00607b JMP Jump 00610b JV Jump if oVerflow 00611b JNV Jump if No oVerflow 00612b JC Jump if Carry 00613b JNC Jump if No Carry
are the available instructions of this form.
Note that these instructions do provide a four-bit field to indicate which of the availble condition code fields is tested for the branch.
The fifth line shows the format of the subroutine jump instruction placed within the opcode space for basic memory-reference instructions.
One instruction in this category is currently defined:
007dxb JSR Jump to Subroutine
It transfers control to the instruction at the effective address formed by the address field and the base register specified in the sB field, with possible indexing as indicated in the sX field; and it stores the return address, which is the address of the following halfword, in the base register indicated by the dB field.
Thus, the destination base register can be used with a zero displacement in a jump instruction to return from the subroutine.