This page discusses a successor to the Concertina architecture.
The original Concertina architecture grew out of a small page explaining the basic idea of how a computer works, using an architecture resembling typical historic CISC architectures as an example. And then various features were added, to illustrate how they worked.
This architecture has been designed with modern performance considerations in mind, such as how the overhead involved in out-of-order execution led to a transition to RISC architectures, but with some of the elements of the original RISC concept being discarded.
The following diagram contains a comprehensive overview of the instruction formats used in this architecture:
(Note that it is 2248 pixels in width, and thus it may be necessary to scroll on your browser to see parts of it.)
The instruction formats are organized in four columns, each one referring to a different mode of operation of the system.
Only the first column shows the complete set of instruction formats available in the first mode; the remaining columns are primarily concerned with the instructions which replace the standard memory-reference instructions of the first mode, although 16-bit instructions are shown in those columns as well, since those instructions are also changed along with the mode.
In the four different modes, the meaning of instructions may change, but the length of an instruction associated with a particular pattern of bits does not change.
In the first column, illustrating mode 00, the basis of instruction length decoding is visible.
The basic portion of the instruction set is shown in the upper left corner, enclosed by a box with dotted lines.
A standard memory-reference instruction consists of these fields:
A seven bit opcode, which may begin with 00, 01, or 10, but not 11.
A three-bit field indicating the destination register of the instruction.
A three-bit field indicating the index register used by the instruction. If this field contains zero, the instruction's source operand in memory is not indexed.
A three-bit field indicating the base register used by the instruction. If this field contains zero, then the instruction is not a memory-reference instruction, and is instead only 16 bits long, as it does not contain an address.
Register-to-register instructions use the field that would be the index register field to indicate the source register of the instruction.
Instructions starting with 11 are divided into two groups.
Those which begin with 110 are additional 16-bit instructions. These instructions allow a shift instruction, and a short-range conditional branch instruction, to be encoded in only 16 bits.
Those which begin with 111 are 48-bit instructions. These allow memory-to-memory instructions for packed decimal arithmetic and string operations to be encoded in only 48 bits. In order to achieve this, both the source and destination memory operands must use the same base register, and this base register may be either base register 6 or base register 7, as indicated by 0 or 1 respectively in the sB field of the instruction.
Other instructions, which may be 16, 32, 48, or 64 bits in length, are indicated by opcodes that would be those of 16-bit register-to-register instructions, except that the source and destination register fields contain the same number.
The development of the memory-reference instructions from one mode to the next, as shown in the diagram, is as follows:
In the first mode, mode 00, memory-reference instructions have full 16-bit addresses, and full 7-bit opcodes. Thus, they can refer to unaligned operands, and they can be arithmetic operate instructions in addition to load-and-store operations.
In the second mode, mode 01, memory-reference instructions must refer to aligned operands. The additional opcode space made available by this restriction is used for additional instructions, including alternate forms of the conditional branch and subroutine call instructions.
In the third mode, mode 10, memory-reference instructions, in addition, may only be load-and-store operations. This does not change the portion of the opcode space allocated to memory-reference instructions, as the additional two bits made available by this are used to allow the destination register to be one of 32 registers instead of one of eight registers.
In the fourth mode, mode 11, memory-reference instructions are also only load-and-store operations, but in addition they once again refer to one of the eight basic registers as their destination register. Here, the two bits made available are used to explicitly indicate which instructions depend on each other.
In the different modes, a different complement of registers is available.
Some special purpose registers are available in all modes.
There are 16 short vector registers which are 256 bits long.
There are 128 floating-point vector registers, each of which contains 64 entries that are 128 bits long.
There are 8 base registers. These are 32 bits long in 32-bit mode, and 64 bits long in 64-bit mode.
Mode 00 is CISC mode.
In this mode, eight arithmetic/index registers, each 32 bits long, and eight floating-point registers, each 128 bits long, are available to the programmer.
In 64-bit mode, using registers 2, 4, or 6 as index registers will indicate 64-bit indexing, using the indicated register to contain the most significant half of the index, and the following register to contain the least significant half of the index.
Mode 10 is RISC mode.
In this mode, an additional set of thirty-two integer arithmetic registers, still 32 bits long, and an additional set of thirty-two floating-point registers, each 128 bits long, are also available to the programmer. The original two sets of eight registers are also available, and it is only the original eight arithmetic/index registers that can be used as index registers.
Mode 11 is DSP mode.
In this mode, in addition to the sets of eight registers and of thirty-two registers, a set of 128 integer arithmetic registers, 32 bits long, and a set of 128 floating-point registers, 128 bits long, are also available.
Mode 11 has other distinguishing characteristics.
In this mode, following the lead of the Control Data 6600, instructions are organized into aligned 64-bit blocks in memory, and they may not cross block boundaries. This facilitates rapid parallel decoding of instructions.
Most instructions contain a U bit and a D bit. These are used to indicate instruction dependencies. If an instruction has its D bit set, this indicates that its execution is dependent upon a result calculated by a previous instruction which has its U bit set.
Note that which U bit corresponds to which D bit is not explicitly indicated, and thus derives from the history of instruction execution. Resynchronization instructions are provided, and should be used at branch entry points.
In the fourth column of the diagram, for mode 11, some instructions are enclosed by boxes with solid lines.
Those are the instructions without U and D bits.
As in mode 11, execution proceeds without interlocks, these instructions can only be employed with extreme caution, and in some implementations, they may not be available, except for the 16-bit instructions shown only in the first column, headed "Special", since those include the instruction to switch between modes.
In the second column of the diagram, for mode 01, some instructions are also shown enclosed by boxes with solid lines. The availability of those instructions in that mode, however, is dynamic, not static.
A program running in mode 00 does not have access to, or posession of, the sets of 32 registers and of 128 registers used in other modes. A program running in mode 10 does not have access to, or possession of, the sets of 128 registers used in mode 11, but must have the sets of 32 registers, as it uses them to access memory. And a program running in mode 11 has all three pairs of sets of registers.
The fact that a program is running in mode 01, however, does not determine which registers are available to that program.
Therefore, mode 01 serves two special purposes.
A program running in another mode can switch to mode 01 to perform additional operations for which instructions are available in that mode, but not in its own mode, without incurring the overhead of changing the register set allocated to its process.
This is particularly useful for programs running in mode 11, where many special operations do not have modified instruction forms which include the U and D bits required to make it convenient for them to work properly, and also for programs running in mode 00, because there, the memory-reference instructions take up a large amount of opcode space, making a number of special 32-bit instructions, defined in other modes, available.
The fact that the register complement is not determined by the mode in the case of mode 01 also makes it the normal mode of choice for interrupt service routines.