15-bit short instructions may occur within programs by means of occurring in pairs within a 32-bit word.
These paired instructions have the formats shown in this diagram:
Line 1 gives the format of the operate instructions for Medium and Double Precision floating-point numbers.
0 10 000 001 SWM SWD 000 0 CM CD 001 1 LM LD 010 2 STM STD 011 3 AM AD 100 4 SM SD 101 5 MM MD 110 6 DM DD 111 7
Line 2 gives the format of the operate instructions for Single Precision and Extended Precision floating-point nubers:
The opcodes for these instructions are:
0 10 0000 0001 SWF SWQ 000 0 CF CQ 001 1 LF LQ 010 2 STF STQ 011 3 AF AQ 100 4 SF SQ 101 5 MF MQ 110 6 DF DQ 111 7
Line 3 gives the format of the operate instructions for integers.
The opcodes for these instructions are:
0 10 20 30 40 50 60 70
0000 0001 0010 0011 0100 0101 0110 0111
SWB IB SWH IH SW I SWL 000 0
CB XB CH XH C X CL XL 001 1
LB ULB LH ULH L UL LL 010 2
STB DUB STH DUH ST DU STL DUL 011 3
AB NB AH NH A N AL NL 100 4
SB OB SH OH S O SL OL 101 5
MB MH MEH M ME ML MEL 110 6
DB DH DEH D DE DL DEL 111 7
The different instructions featured in the first three lines of the diagram are:
For integer types:
M MULTIPLY Multiply the contents of the source and destination locations, placing the
least significant part of the result of the same length as the two input
operands in the destination location, with sign extension if that is shorter
than the length of the destination register
D DIVIDE Divide the contents of the source location by the contents of the destination
location, placing the quotient in the destination location
L LOAD Place the contents of the source operand in the destination register;
if the type involved is smaller than the register, perform sign extension
ST STORE Fill the destination location from the least significant part of the
source location
A ADD Add the contents of the source and destination locations, placing the
result in the destination location
S SUBTRACT Subtract the contents of the source location from those of the destination
location, placing the result in the source location
SW SWAP Exchange the contents of the source and destination locations
C COMPARE Subtract the contents of the source location from the contents of
the destination location, but with the operation modified so that
overflow cannot possibly result, and set the condition codes appropriately
without modifying the destination location
I INSERT Fill the least significant bits of the destination register with
the contents of the source location, leaving the rest of the destination
register unaffected
UL UNSIGNED LOAD Fill the least significant bits of the destination register with
the contents of the source location, and clear the remaining more
significant bits of the destination register
X EXCLUSIVE OR Perform a bitwise Exclusive OR operation between the contents of the source
and destination locations, placing the result in the desination location
N AND Perform a bitwise Logical AND operation between the contents of the source
and destination locations, placing the result in the desination location
O OR Perform a bitwise Logical OR operation between the contents of the source
and destination locations, placing the result in the desination location
ME MULTIPLY EXTENSIBLY Multiply the contents of the source and destination locations. Take the
full product, as an integer having twice the size as that of the source
and the destination, and:
- in the case of the halfword and integer versions of the instruction, place it in the destination
register, with sign extension in the halfword version;
- in the case of the long version of the instruction, place the most significannt half of the result
in the destination register, which must be an even-numbered register, and place the least significant
half of the result in the register following
DE DIVIDE EXTENSIBLY Divide a destination operand of twice the length of that indicated by the
instruction type (and located as the result of the MULTIPLY EXTENSIBLY
instruction) by the source operand; store the double length quotient
in the destination location (again following the MULTIPLY EXTENSIBLY
result placement) and the single length remainder in the next register
following those that are used.
Whenever a result is not wide enough to fill a register, sign extension
is performed.
Division is performed giving a result as if both operands were converted
to positive numbers before starting, with the signs then set afterwards
to give a correct result based on the actual signs of the operands. Thus
both the quotient and the remainder will be positive or zero if the dividend
and divisor have the same sign, and both will be negative or zero if they
are of opposite signs.
The possible integer types, and the suffixes that indicate them, are:
B BYTE An 8-bit two's complement integer
H HALFWORD A 16-bit two's complement integer
INTEGER A 32-bit two's complement integer
L LONG A 64-bit two's complement integer
The integer registers are 64 bits long, to contain the longest of these types.
The available floating-point operations are SWAP, LOAD, STORE, ADD, SUBTRACT, MULTIPLY, and DIVIDE. Their functions are basically the same as those of the corresponding integer operations, except that floating-point arithmetic is performed.
The possible floating-point types for 16-bit instructions, and the suffixes that indicate them, are:
M MEDIUM A 48-bit floating-point number (preferably aligned on 16-bit boundaries) F FLOATING A 32-bit floating-point number D DOUBLE A 64-bit floating-point number
with a common floating-point type used in other instructions being
Q QUAD A 128-bit floating-point number
with their formats as indicated within this diagram:
Note that in the diagram, exponents for the types other than the 128-bit internal type are given as excess-126, excess-510, and excess-1022; documentation for the IEEE 754 standard, and most descriptions of it, refer to the exponents as excess-127, excess-511, and excess-1023 instead. This is because these accounts place the binary point of the mantissa in front of its first visible bit, while I place it in front of the hidden first bit to remain in accord with the convention used in most other floating-point formats that the mantissa is in the range [0.1). In the case of the 128-bit internal form, as the first bit of the mantissa is now the bit which would have been the hidden bit, since for the other forms, I had been placing the binary point in front of the hidden bit, the offset is consistent by remaining two less than a power of two; this would need to be the case even if I had used the normal convention for the exponents of the other formats.
The 128-bit type of this architecture is similar to 80-bit temporary real, but with both a longer exponent and a longer mantissa.
New standards for 128-bit and 256-bit reals have been added to the IEEE 754 standard. These types are supported within the Short Vector instructions, which do not use an expanded internal form for real numbers or other data types. There will also be instructions using the floating-point registers to work with these types, which is why the exponent of the ordinary 128-bit floating-point type has been made long enough to support the IEEE 754 256-bit floating type.
These instructions are then also suffixed RC for Register Compact to indicate the addressing mode.
The remaining instructions to be described below may only appear as the second of two short instructions within a 32-bit word, in order to reserve opcode space for 64-bit or longer instructions.
Lines 4 through 7 of the diagram illustrate the shift and rotate short instructions. They are:
60x0x LSLLC Logical Shift Left Long Compact
60x1x LSRLC Logical Shift Right Long Compact
60x2x RLLC Rotate Left Long Compact
60x3x ASRLC Arithmetic Shift Right Long Compact
64x0x LSLC Logical Shift Left Compact
64x1x LSRC Logical Shift Right Compact
64x2x RLC Rotate Left Compact
64x3x ASRC Arithmetic Shift Right Compact
66x0x LSLHC Logical Shift Left Halfword Compact
66x1x LSRHC Logical Shift Right Halfword Compact
66x2x RLHC Rotate Left Halfword Compact
66x3x ASRHC Arithmetic Shift Right Halfword Compact
6700x LSLBC Logical Shift Left Byte Compact
6701x LSRBC Logical Shift Right Byte Compact
6702x RLBC Rotate Left Byte Compact
6703x ASRBC Arithmetic Shift Right Byte Compact
Logical right and left shifts insert zeroes; the arithmetic right shift inserts a copy of the existing value of the most significant bit into the leftmost position of the word so as to maintain the sign as either negative or non-negative.
An arithmetic left shift inserts zeroes into the leftmost end of a number regardless of its sign, just like a logical left shift, but it differs in that the overflow bit is set if a left shift results in a change of the sign of the value being shifted, instead of merely a carry out of that value; this difference is, however, not applicable to short instructions, as they may not alter the condition codes, not having space for a C bit.
Line 8 of the diagram shows the branch instructions, which have the following opcodes:
704xx BL Branch if Low
710xx BE Branch if Equal
714xx BLE Branch if Low or Equal
720xx BH Branch if High
724xx BNE Branch if Not Equal
730xx BHE Branch if High or Equal
734xx BNV Branch if No Overflow
740xx BV Branch if Overflow
750xx BC Branch if Carry
754xx BNC Branch if No Carry
774xx B Branch
Unused values are used instead for the set flag instructions in line 9, as follows:
700xx CTF Condition to Flag Set flag to 1 if condition valid; set flag to 0 if condition not met
760xx SFC Set Flag on Condition Set flag to 1 if condition met; leave it unaffected otherwise
764xx CFC Clear Flag on Condition Set flag to 0 if condition met; leave it unaffected otherwise
Line 10 of the diagram shows the format of one special instruction:
7440x SRA Store Return Address
This 16-bit instruction saves the address of the instruction following it, just as a Jump to Subroutine instruction would do, but without branching. It is useful for initializing a base register at the beginning of a subroutine. Of course, a Jump to Subroutine with a program-relative displacement as its address may also be used for that purpose.
Line 11 of the diagram shows the format of another special instruction:
770xx SVC Supervisor Call
This instruction performs the equivalent of an interrupt from within software, allowing portions of the operating system not running in supervisor state to request services from the kernel, as well as possibly also allowing user programs to request services from the operating system.
Line 10 of the diagram shows the format of an instruction which saves a pointer to the location following the instruction, in the same manner as a subroutine call instruction, but without branching. This is an important instruction for use at the beginning of a program, subroutine, or function, to allow its first base register to be initialized.