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Basic Opcodes

As seen on the previous page, the instruction formats for this architecture are as shown below:



The 16-bit instructions

The first line shows the format of sixteen-bit register-to-register instructions.

These operate on banks of 32 registers. The source register is indicated by a field that is only three bits long; this is achieved by requiring that the source and destination registers both belong to the same one of four groups of eight registers: registers 0 to 7, registers 8 to 15, registers 16 to 23, and registers 24 to 31.

In order to ensure that at least six opcode bits are available, which means that the instruction format is still only used for instructions dealing only with the most common integer and floating-point types, but is not overly restricted, while all other operate instructions, as is common in many RISC architectures, reserve a bit for indicating if the instruction is allowed to affect the condition codes, 16-bit operate instructions may not alter the condition codes.

The opcode bits have the following significance:

 000   001   010   011   100   101   110   111
 SWH   IH    SW    I     SWM   SWF   SWD   SWQ   000
                                                 001
 LH    ULH   L     UL    LM    LF    LD    LQ    010
 STH   XH    ST    X     STM   STF   STD   STQ   011
 AH    NH    A     N     AM    AF    AD    AQ    100
 SH    OH    S     O     SM    SF    SD    SQ    101
 MH    MEH   M     ME    MM    MF    MD    MQ    110
 DH    DEH   D     DE    DM    DF    DD    DQ    111

applying the types:

Fixed-point:

H  Halfword   16 bits
   Integer    32 bits

Floating-point:

M  Medium     48 bits (16-bit aligned)
F  Floating   32 bits
D  Double     64 bits
Q  Quad      128 bits

to the operations:

SW  Swap

L   Load
ST  Store
A   Add
S   Subtract
M   Multiply
D   Divide

I   Insert

UL  Unsigned Load
X   Exclusive OR
N   AND
O   OR
ME  Multiply Extensibly
DE  Divide Extensibly

As on the System/360, Load performs sign extension of fixed-point quantities. Insert instead loads the operand into the least significant part of the destination register without changing the most significant part, and Unsigned Load clears the most significant part.

Multiply Extensibly produces a product that is twice the length of its terms.

Divide Extensibly involves a dividend that is twice the length of the divisor; both the quotient and the remainder are also twice as long as the divisor. Except for Divide Extensibly Long (not part of this group of instructions, but which is available in other instruction formats), the remainder is in the destination register, and the quotient is placed in the following register; in the case of Divide Extensibly Long, as the divisor is a 64 bit integer, the dividend, remainder, and quotient are all contained in register pairs.

Instructions that have the same register as source and destination are not allowed in this format, permitting a small number of additional 16-bit instructions.


The second line of the diagram shows the format of instructions that set one of seven predication flags based on the status of the condition codes. The field in this instruction that indicates the condition to test for has the same interpretation as that in the conditional branch instructions. These instruction are:

00 00 0000 00  CFL   Clear Flag
00 00 0001 00  SFLT  Set Flag if Less Than
00 00 0010 00  SFEQ  Set Flag if Equal
00 00 0011 00  SFLE  Set Flag if Less than or Equal
00 00 0100 00  SFGT  Set Flag if Greater Than
00 00 0101 00  SFNE  Set Flag if Not Equal
00 00 0110 00  SFGE  Set Flag if Greater than or Equal
00 00 0111 00  SFL   Set Flag

00 00 1000 00  SFV   Set Flag if oVerflow
00 00 1001 00  SFNV  Set Flag if No oVerflow
00 00 1010 00  SFC   Set Flag if Carry
00 00 1011 00  SFNC  Set Flag if No Carry

Note that the flag field is repeated twice. Register-to-register instructions that have the same source and destination registers are not permitted, and, since the first two bits of the destination register field are also applied to the three bits of the source register field, when the last three bits of the destination register field are the same as the contents of the source register field, both fields would reference the same register.

Thus, the fact that the flag field is repeated is what indicates that this is not a 16-bit register-to-register instruction. As having the flag bits all zero indicates an instruction is not predicated, a zero value in both positions indicates the type of instruction seen in the next line of the diagram.


The third line of the diagram shows an instruction the purpose of which is to indicate, for DSP instructions, which U bit, indicating an instruction upon which there is a dependency, corresponds to which D bit, indicating a dependent instruction. The offset field contains a value from 0 to 7, indicating the number of set D bits to skip prior to the first set D bit following this instruction, after the set U bit, which may have preceded this instruction, to which it corresponds.

This instruction is:

00 00 ccc ooo 000 000   SEO   Set Offset

It is important to re-establish this synchronization at those points in the code which serve as branch targets, or dependencies will not be processed correctly.

Instruction code is to behave as if it is fetched from memory in blocks of 256 bits, as some implementations may do this to facilitate both more rapid decoding and superscalar operation. These blocks are aligned on 256-bit boundaries; that is, they begin on a byte the address of which ends in five zeroes.

The configuration field is used to speed decoding of the following block of instructions, if that block is composed of five 48-bit DSP instructions and one 16-bit instruction (presumably another Set Offset instruction). Its contents indicate as follows how the next block will be laid out:

0 [1][   3   ][   3   ][   3   ][   3   ][   3   ]
1 [   3   ][1][   3   ][   3   ][   3   ][   3   ]
2 [   3   ][   3   ][1][   3   ][   3   ][   3   ]
3 [   3   ][   3   ][   3   ][1][   3   ][   3   ]
4 [   3   ][   3   ][   3   ][   3   ][1][   3   ]
5 [   3   ][   3   ][   3   ][   3   ][   3   ][1]
6 [1][   3   ][1][   3   ][1][   3   ][1][   3   ]

The values from 0 to 5 allow a single 16-bit instruction to be in any position, and the value 6 permits a block of DSP instructions to have multiple branch targets within it.

If the configuration field contains 7, this means that no layout is imposed on the following block.

This instruction may be placed at any position in the block because if there is a branch target within DSP code, it should be this instruction rather than the following DSP instruction to which the branch points - therefore, this instruction must be able to immediately precede any of the DSP instructions, since any of them may be the instruction that is next desired to be executed in the control flow.

It is specifically because the length of instructions, being indicated at the start of an instruction rather than the end, can only be determined moving forwards from a given address known to be the start of an instruction; the address portion of a 32-bit instruction can also be a valid 16-bit instruction, for example, so that there is no way to scan backwards to find a Set Offset instruction earlier in a block, that this type of instruction must be the actual branch target, and must be placed immediately before the instruction to which it is desired to pass control flow.

As may be expected, this implies that this instruction only speeds the decoding of the instructions in the following block when it is reached by fall-through; when an instruction within a block is reached by a branch, the lengths of the instructions from the branch point onwards within that block must be determined in the conventional sequential manner.

This instruction is not defined as overriding the normal length indications; if the leading bits of the opcodes of the instructions in the next block do not correspond to the lengths indicated, an error condition may result; but the behavior is undefined; for example, there may be a fall-back to normal sequential decoding, or the lengths may be treated as an override.

The reason the behavior is left as undefined instead of being specified is to permit the most efficient implementation of the normal case, when the indicated lengths do match the indication, so that the maximum gains, or minimum losses, in speed result from the use of the instruction, whatever techniques may be used for the implementation of the architecture.


This is one of two ways in which instructions may be arranged to permit rapid decoding, without the need to serially proceed through instructions one at a time to determine from one instruction where the next one begins. In addition to rapid decoding, this is intended to be used with those 48-bit instructions that contain a U bit and a D bit, thus explicitly indicating instructions that may be executed in parallel, allowing functionality similar to that provided in DSP designs.

It should also be noted that, because the length is indicated in a simple fashion, with instructions beginning with 0 being 16 bits long, instructions beginning with 10 being 32 bits long, and instructins beginning with 11 being 48 bits long, determining where each instruction begins in a number of instructions in a wide fetch from memory should only take a limited number of gate delays, as opposed to multiple cycles.

The other way in which instructions can be arranged to allow for more rapid decoding is to use only 32-bit instructions, possibly accompanied by 16-bit instructions in pairs. This is a feasible option because the 32-bit instructions alone are a reasonably complete instruction set, and it provides performance comparable to conventional RISC architectures.

It is intended that implementations will attempt to accelerate decoding both in the case of exclusive sequences of 32-bit instructions aligned on 32-bit boundaries, and exclusive sequences 32-bit instructions which begin on odd 16-bit boundaries, so that occasional 48-bit or 16-bit instructions in a program primarily composed of 32-bit instructions will not slow down the decoding of instructions in later blocks, without the need for padding with 16-bit no-operation instructions.


As noted, instruction code is to behave as if it is fetched from memory in aligned blocks of 256 bits, as some implementations may do this to facilitate both more rapid decoding and superscalar operation.

This fact needs to be kept in mind to understand the function of the instructions the format of which appears in the fourth and fifth lines of the diagram.

The fourth line shows the format of an instruction that is normally automatically generated by an assembler rather than being explicitly specified by a programmer.

Its function is to instruct the computer, when fetching the 256-bit block of instruction code following the one in which this instruction is found, to ignore the last one to fifteen 16-bit instruction syllables in that block when decoding and executing instructions.

This applies to the block physically following; thus, it has no effect if a branch away takes place before control would come to the address of the skipped-over area, and it means that abnormal results would take place if a branch were to have, as its target, an address following an instruction of this type up to the end of the following block.

The instruction has the code 00 01 ssss 00 000000.

The fifth line shows the format of another instruction that is normally automatically generated by an assembler rather than being explicitly specified by a programmer, and which is designed to work together with the instruction shown in the fourth line.

The effect of this instruction is to take a string of 16-bit instruction syllables, from one to seven instruction syllables long, as indicated by the repeated size field, and execute them as an instruction of that length. This means that the first few bits of the instruction do not determine its length, and this allows additional instructions from one to four syllables in length to be provided, as well as allowing instructions from five to seven syllables long to be defined as well.

Among other things, this allows immediate operate instructions with 64-bit immediate operands to be provided for.

The beginning of the string of instruction syllables is indicated by the pointer field. The number in that field, if from 0 to 15, indicates one of the instruction syllables in the 256-bit block of instruction code immediately preceding the one in which this instruction is found; if from 16 to 31, it indicates one of the instruction syllables in the same block as that in which this instruction is contained.

Note that an area of space reserved by the instruction the format of which was shown in the preceding line of the diagram can contain two or more different instructions intended for execution by this instruction.

The 32-bit instructions

The sixth through twelfth lines of the diagram show the format of those basic memory-reference instructions which utilize the short base registers. These instructions may reference unaligned operands.

Instructions of this format begin with the prefix bit 1, indicating an instruction 32 bits in length.

Next is a five-bit opcode; for reasons of pipeline efficiency, as well as to allow access to as many data types as possible, following RISC practice, this format is used only for load and store instructions. However, in addition to the normal Load instruction, which performs sign extension for integer operands, Unsigned Load and Insert are provided as well for integer data types shorter than the arithmetic-index registers.

The opcode is followed by two 1 bits to distinguish this type of instruction from the memory-reference instructions that use the long base registers as well as from some of the multiple-register load and store instructions.

Next is a five-bit field indicating the destination register for the instruction. In the case of store instructions, the register indicated by that field serves as the source operand, of course.

Then there is a three-bit index register field. It is interpreted as follows:

Field   Register used for indexing
value

  0     No indexing
  1      1
  2      2
  3      3
  4      4/12/20/28
  5      5/13/21/29
  6      6/14/22/30
  7      7/15/23/31

Thus, the value zero indicates that the address is not indexed; other values in the first half refer to index registers shared among all subthreads working in different groups of eight registers, and values in the second half refer to index registers in the same group of eight registers as the destination register (or, in the case of floating-point instructions, the corresponding group of eight registers).

The basic memory-reference instruction format occupies six lines of the diagram as there are six possible formats for the address constant portion of these instructions, as well as all other instructions which reference main memory with the aid of the short base registers.

In the first address constant format, the fifteen-bit address field is an unsigned positive displacement which is added to the contents of base register zero to form the effective address of the instruction (additionally subject to indexing, if specified).

In the second address constant format also uses base register zero. In this case, the eleven-bit address field of the instruction is shifted left by two bits (in the case of 32-bit addressing) or three bits (in the case of 64-bit addressing) before being added to the contents of base register zero to indicate the memory location containing the address to use for the instruction itself. If indexing is indicated, the contents of the index register are then added to that address to form the effective address of the instruction.

This is post-indexed indirect addressing; it is provided so that a program can make use of multiple large arrays without having to reserve one base register as a pointer to each array.

The third address constant format, the eleven-bit displacement field contains a signed two's complement number which is relative to the contents of the program counter. A value of zero corresponds to the address of the byte immediately following the end of the instruction.

The fourth address constant format allows an address contained in an integer register to be used instead of one produced by adding a displacement to the content of a base register; this is register indirect addressing. The fifth address constant format is similar, but also causes the contents of that register to be incremented by the size of the operand after use; this is auto-increment register indirect addressing.

The sixth address constant format is used to permit the source operand of an instruction to be an eight-bit immediate operand. (Of course, the usefulness of this is limited by the fact that address constants are used for memory-reference instructions, which are usually only load and store instructions.)

The seventh address constant format uses base registers 1 through 7; their contents are added to the twelve-bit address field to form the effective address of the instruction.

It is intended that base register zero will be used to point to the local storage of a program, and the other base registers from 1 to 7 will be used for tasks such as passing parameters when calling subroutines, accessing storage shared between routines, and so on.


Allowing address constants which include a base register specification to fit into 16 bits, while also allowing the displacement field to be 15 bits long in one case instead of only 12 bits long, as is the case for most choices of base register, in this fashion is, of course, inspired by the IBM System/360 Model 20. As well, the additional addressing modes which are offered of register indirect addressing and auto-increment register indirect addressing take their inspiration from those offered on the DEC PDP-11 computer and the later TI 9900 microprocessor.


The instructions provided in this format are:

1 00000 11  LB    Load Byte                    (8-bit integer)
1 00001 11  STB   Store Byte
1 00010 11  ULB   Unsigned Load Byte
1 00011 11  IB    Insert Byte

1 00100 11  LH    Load Halfword                (16-bit integer)
1 00101 11  STH   Store Halfword
1 00110 11  ULH   Unsigned Load Halfword
1 00111 11  IH    Insert Halfword

1 01000 11  L     Load                         (32-bit integer)
1 01001 11  ST    Store
1 01010 11  UL    Unsigned Load
1 01011 11  I     Insert

1 01100 11  LL    Load Long                    (64-bit integer)
1 01101 11  STL   Store Long

1 10000 11  LC    Load Classic                 (40-bit float)
1 10001 11  STC   Store Classic

1 10010 11  LM    Load Medium                  (48-bit float)
1 10011 11  STM   Store Medium

1 10100 11  LF    Load Floating                (32-bit float)
1 10101 11  STF   Store Floating

1 10110 11  LD    Load Double                  (64-bit float)
1 10111 11  STD   Store Double

1 11000 11  LQ    Load Quad (Extended)         (128-bit float)
1 11001 11  STQ   Store Quad

Note that several floating-point types are not accessible by instructions in this format, and instead require the use of the 48-bit Supplementary Memory-Reference instruction format.


The thirteenth through twenty-second lines of the diagram illustrate the memory-reference instructions which use the long base registers.

After the 1 which indicates a 32-bit instuction, a five bit destination register field is present.

After the opcode bits, there is a three-bit index register field. It is interpreted in the same fashion as the three-bit index register fields of the memory-reference instructions using the short base registers:

Field   Register used for indexing
value

  0     No indexing
  1      1
  2      2
  3      3
  4      4/12/20/28
  5      5/13/21/29
  6      6/14/22/30
  7      7/15/23/31

The value zero indicates that the address is not indexed; other values in the first half refer to index registers shared among all subthreads working in different groups of eight registers, and values in the second half refer to index registers in the same group of eight registers as the destination register (or, in the case of floating-point instructions, the corresponding group of eight registers).

Note that all eight long base registers are used as base registers; specifying zero in the base register field does not indicate absolute addressing.

These instructions use the opcodes, here shown with the prefix bits and the address postfix bits, if applicable, included:

1 rrrrr 00 00              LB     Load Byte
1 rrrrr 00 01              STB    Store Byte
1 rrrrr 00 10              ULB    Unsigned Load Byte
1 rrrrr 00 11              IB     Insert Byte

1 rrrrr 01 00 ...     0    LH     Load Halfword
1 rrrrr 01 01 ...     0    STH    Store Halfword       
1 rrrrr 01 10 ...     0    ULH    Unsigned Load Halfword
1 rrrrr 01 11 ...     0    IH     Insert Halfword

1 rrrrr 01 00 ...    01    L      Load
1 rrrrr 01 01 ...    01    ST     Store   
1 rrrrr 01 10 ...    01    UL     Unsigned
1 rrrrr 01 11 ...    01    I      Insert

1 rrrrr 01 00 ...   011    LL     Load Long
1 rrrrr 01 01 ...   011    STL    Store Long

1 rrrrr 100 0              LC     Load Classic
1 rrrrr 100 1              STC    Store Classic

1 rrrrr 101 0 ...     0    LM     Load Medium
1 rrrrr 101 1 ...     0    STM    Store Medium       

1 rrrrr 101 0 ...    01    LF     Load Floating
1 rrrrr 101 1 ...    01    STF    Store Floating       

1 rrrrr 101 0 ...   011    LD     Load Double
1 rrrrr 101 1 ...   011    STD    Store Double      

1 rrrrr 101 0 ...  0111    LQ     Load Quad (Extended)
1 rrrrr 101 1 ...  0111    STQ    Store Quad       

1 rrrrr 101 0 ... 01111    LO     Load Octuple (Double Extended)
1 rrrrr 101 1 ... 01111    STO    Store Octuple      

These instructions can access only a limited number of floating-point data types, because of limitations in the amount of opcode space available to them. As well, the choice of which data types to support in this format is determined by the fact that they conserve opcode space by accessing only aligned operands.


The scheme of using the last few bits, which would otherwise be unused if only aligned operands are addressed, of the displacement field in an instruction to allow the same opcode bits to be used for instructions dealing with different data types was used by the Systems Engineering Laboratories SEL 32 computer, as I have acknowledged elsewhere for other designs of mine as well.


The twenty-third and twenty-fourth lines show the formats of the conditional jump instructions. With these instructions, the condition code field can be thought of as part of the opcode of the instruction.

The instructions the format of which is shown in the twenty-second line have an index register field, but they do not have a destination register field. The subroutine jump instructions which specify an index register, shown in the twenty-fifth line of the diagram, to be described below, do indicate a base register as the destination register in which the return address is stored, but this is also not relevant to indicating a group of eight arithmetic-index registers within the complement of thirty-two such registers.

Thus, for these instructions, the index register field either indicates no indexing, if it is zero, or indicates that the index register is one of registers 1 through 7. Since branching affects all subthreads, no attempt has been made to distribute the index register assignments through the four groups of eight arithmetic-index registers.

The opcodes of the conditional jump instructions described in the twenty-third line of the diagram are:

01 0 101 00 0000 0  NOP  No Operation
01 0 101 00 0001 0  JLT  Jump if Less Than
01 0 101 00 0010 0  JEQ  Jump if Equal
01 0 101 00 0011 0  JLE  Jump if Less than or Equal
01 0 101 00 0100 0  JGT  Jump if Greater Than
01 0 101 00 0101 0  JNE  Jump if Not Equal
01 0 101 00 0110 0  JGE  Jump if Greater than or Equal
01 0 101 00 0111 0  JMP  Jump

01 0 101 00 1000 0  JV   Jump if oVerflow
01 0 101 00 1001 0  JNV  Jump if No oVerflow
01 0 101 00 1010 0  JC   Jump if Carry
01 0 101 00 1011 0  JNC  Jump if No Carry

In addition, conditional jump instructions of the form 01 0 101 00 cccc 1 are provided; the format of these instructions is shown in the twenty-fourth line of the diagram. These instructions use the long base registers, and may not be indexed.


The twenty-fifth and twenty-sixth lines show the format of the subroutine jump instructions.

These instructions have the opcodes:

01 1 101 0000     JSR      Jump to Subroutine
01 1 101 0001     JSRLR    Jump to Subroutine Long Return
01 1 101 0010     JSRYR    Jump to Subroutine Extended Return

01 1 101 0100     JSR      Jump to Subroutine
01 1 101 0101     JSRLR    Jump to Subroutine Long Return
01 1 101 0110     JSRYR    Jump to Subroutine Extended Return

thus, the return address may be placed in any of the three types of base register available, independently of the type of base register used for the address of the instruction.

Note that the mnemonics of these instructions are not changed by the type of base register used in forming the address of their branch targets, as that is implicit from which base registers were declared to be used to address the storage in which they are contained.


The twenty-seventh line shows the format of the shift instructions.

The available instructions are:

01 c 101 11100 ddddd  00000000   SLB     Shift Left Byte
01 c 101 11100 ddddd  00000001   SRB     Shift Right Byte

01 c 101 11100 ddddd  00000011   ASRB    Arithmetic Shift Right Byte

01 c 101 11100 ddddd  00000100   ROLB    Rotate Left Byte
01 c 101 11100 ddddd  00000101   RORB    Rotate Right Byte
01 c 101 11100 ddddd  00000110   RLCB    Rotate Left through Carry Byte
01 c 101 11100 ddddd  00000111   RRCB    Rotate Right through Carry Byte

01 c 101 11100 ddddd  00001000   SLH     Shift Left Halfword
01 c 101 11100 ddddd  00001001   SRH     Shift Rig ht Halfword

01 c 101 11100 ddddd  00001011   ASRH    Arithmetic Shift Right Halfword

01 c 101 11100 ddddd  00001100   ROLH    Rotate Left Halfword
01 c 101 11100 ddddd  00001101   RORH    Rotate Right Halfword
01 c 101 11100 ddddd  00001110   RLCH    Rotate Left through Carry Halfword
01 c 101 11100 ddddd  00001111   RRCH    Rotate Right through Carry Halfword

01 c 101 11100 ddddd  00010000   SL      Shift Left
01 c 101 11100 ddddd  00010001   SR      Shift Right

01 c 101 11100 ddddd  00010011   ASR     Arithmetic Shift Right

01 c 101 11100 ddddd  00010100   ROL     Rotate Left
01 c 101 11100 ddddd  00010101   ROR     Rotate Right
01 c 101 11100 ddddd  00010110   RLC     Rotate Left through Carry
01 c 101 11100 ddddd  00010111   RRC     Rotate Right through Carry

01 c 101 11100 ddddd  00011000   SLL     Shift Left Long
01 c 101 11100 ddddd  00011001   SRL     Shift Right Long

01 c 101 11100 ddddd  00011011   ASRL    Arithmetic Shift Right Long

01 c 101 11100 ddddd  00011100   ROLL    Rotate Left Long
01 c 101 11100 ddddd  00011101   RORL    Rotate Right Long
01 c 101 11100 ddddd  00011110   RLCL    Rotate Left through Carry Long
01 c 101 11100 ddddd  00011111   RRCL    Rotate Right through Carry Long

Note that the instructions in the twenty-eighth through thirty-second lines have a large number of opcode bits in their first 16 bits. This will allow all of these instructions to begin with the bits 01 c 101 1111.

The twenty-eighth line shows the format of three-address register-to-register arithmetic instructions. These allow more operations, and more flexibility in performing those operations, than is available from the 16-bit register-to-register arithmetic instructions. They will be described on a later page, as there are a considerable number of these instructions, covering a large number of data formats.


The twenty-ninth line shows the format of additional two-address register-to-register arithmetic instructions; these are intended to provide sufficient opcode space for a wide variety of operations on a wide variety of data types.


The thirtieth line shows the format of instructions which perform various operations on a single operand contained in one register; these will also be described on a later page for the same reason as those the format of which was shown on the preceding two lines.


The thirty-first and thirty-second lines show the format of regular instructions which access the banks of 128 registers used primarily for DSP-type instructions.

These instructions are normal instructions, not DSP instructions, so they do not have a D bit, as their execution is delayed if necessary due to a dependency by means of the normal interlock mechanism. But they do have a U bit, because they can affect the contents of DSP registers, and thus a DSP instruction could be dependent on their completion.

For purposes of associating a U bit with its corresponding D bit, such an instruction behaves as a DSP instruction with the D bit set to zero.


The thirty-second through thirty-fourth lines show the format of multiple-register load and store instructions. These are useful to save and restore the registers at the beginning and end of subroutines.

The thirty-third line shows the instructions that save and restore the arithmetic-index registers and the floating-point registers, as well as those that save and restore the four groups of eight base registers as a single unit of thirty-two base registers:

1 11100 11   LML    Load Multiple Long
1 11101 11   STML   Store Multiple Long
1 11110 11   LMQ    Load Multiple Quad
1 11111 11   STMQ   Store Multiple Quad
1 11010 11   LMB    Load Multiple Base
1 11011 11   STMB   Store Multiple Base

The thirty-fourth line shows the instructions that save and restore the short vector registers:

1 01110 11      LMSV   Load Multiple Short Vector
1 01111 11      STMSV  Store Multiple Short Vector

The thirty-fifth line shows the instructions that save and restore individual sets of eight base registers:

01 0 101 1000   LMSB    Load Multiple Short Base
01 1 101 1000   STMSB   Store Multiple Short Base
01 0 101 1001   LMLB    Load Multiple Long Base
01 1 101 1001   STMLB   Store Multiple Long Base
01 0 101 1010   LMEB    Load Multiple Extended Base
01 1 101 1010   STMEB   Store Multiple Extended Base
01 0 101 1011   LMCB    Load Multiple Code Base
01 1 101 1011   STMCB   Store Multiple Code Base

All the base registers are 64 bits wide; the terms Short, Long, and Extended in connection with these instructions refer to the size of the areas in memory to which they point: 4,096 bytes for short base registers 1 through 7 and 32,768 bytes for short base register 0, 65,536 bytes for all the long base registers, and 1,048,576 bytes for the extended base registers.

Thus, the short base registers correspond to base registers in the IBM System/360 computer, the long base registers to address registers or segment registers in many popular microcomputer architectures, and the extended base registers correspond to the alternate potential function of base registers in current IBM mainframes which implement z/Architecture for instructions in the RXY, RSY, and SIY formats.


The 48-bit instructions

The thirty-sixth line shows the format of the first type of 48-bit instruction that we encounter, the string instructions.

The available string instructions are:

01 c 0 0000   T    Translate
01 c 0 0001   CC   Compare Character
01 c 0 0010   MVC  Move Character
01 c 0 0011   TT   Translate and Test
01 c 0 0100   P    Pack
01 c 0 0101   UP   Unpack
01 c 0 0110   E    Edit
01 c 0 0111   EM   Edit and Mark

For the Translate instruction, the source operation is the translate table 256 bytes in length, and the destination operand is the string to be transformed in place.

The thirty-seventh line shows the format of the packed decimal instructions:

01 c 0 1001   CP   Compare Packed
01 c 0 1010   MVP  Move Packed

01 c 0 1100   AP   Add Packed
01 c 0 1101   SP   Subtract Packed
01 c 0 1110   MP   Multiply Packed
01 c 0 1111   DP   Divide Packed

The thirty-eighth line shows the format of some of the operate instructions with immediate operands that are 32 bits in length. The instructions of this format are:

01 c 0 1000001  CI   Compare Immediate
01 0 0 1000010  LI   Load Immediate

01 c 0 1000100  AI   Add Immediate
01 c 0 1000101  SI   Subtract Immediate
01 c 0 1000110  MI   Multiply Immediate
01 c 0 1000111  DI   Divide Immediate

01 c 0 1011001  CFI  Compare Floating Immediate
01 0 0 1011010  LFI  Load Floating Immediate

01 c 0 1011100  AFI  Add Floating Immediate
01 c 0 1011101  SFI  Subtract Floating Immediate
01 c 0 1011110  MFI  Multiply Floating Immediate
01 c 0 1011111  DFI  Divide Floating Immediate

The thirty-ninth line shows the format of the short vector arithmetic instructions, which will be described in detail in a later section.


The fortieth line shows the format of the long vector register-to-register instructions, and the forty-first and forty-second lines show the formats of the long vector memory-reference instructions. As there are quite a few of these, they will also be dealt with on a later page.


The forty-third and forty-fourth lines show instructions that use the full set of memory-reference instructions, and the forty-fifth line instructions using the full-set of load/store memory reference instructions. Thus, these, as well, will be discussed on a later page.


The forty-sixth through forty-ninth lines show the format of instructions which convert between a binary integer stored in an arithmetic/index register and a packed decimal number in memory. These instructions have the opcodes:

01 c 100 000000 llll  00000000000   PTB   Packed to Byte
01 c 100 000000 llll  00000000001   BTP   Byte to Packed
01 c 100 000000 llll  00000000010   PTH   Packed to Halfword
01 c 100 000000 llll  00000000011   HTP   Halfword to Packed
01 c 100 000000 llll  00000000100   PTI   Packed to Integer
01 c 100 000000 llll  00000000101   ITP   Integer to Packed
01 c 100 000000 llll  00000000110   PTL   Packed to Long
01 c 100 000000 llll  00000000111   LTP   Long to Packed

01 c 100 000000 llll  0 rrrrr 0000000   PTB   Packed to Byte
01 c 100 000000 llll  0 rrrrr 0000001   BTP   Byte to Packed
01 c 100 000000 llll  0 rrrrr 0000010   PTH   Packed to Halfword
01 c 100 000000 llll  0 rrrrr 0000011   HTP   Halfword to Packed
01 c 100 000000 llll  0 rrrrr 0000100   PTI   Packed to Integer
01 c 100 000000 llll  0 rrrrr 0000101   ITP   Integer to Packed
01 c 100 000000 llll  0 rrrrr 0000110   PTL   Packed to Long
01 c 100 000000 llll  0 rrrrr 0000111   LTP   Long to Packed

01 c 100 000000 llll  1 rrrrr 0 bbb 00   PTB   Packed to Byte
01 c 100 000000 llll  1 rrrrr 0 bbb 01   BTP   Byte to Packed
01 c 100 000000 llll  1 rrrrr 0 bbb 10   PTH   Packed to Halfword
01 c 100 000000 llll  1 rrrrr 0 bbb 11   HTP   Halfword to Packed
01 c 100 000000 llll  1 rrrrr 1 bbb 00   PTI   Packed to Integer
01 c 100 000000 llll  1 rrrrr 1 bbb 01   ITP   Integer to Packed
01 c 100 000000 llll  1 rrrrr 1 bbb 10   PTL   Packed to Long
01 c 100 000000 llll  1 rrrrr 1 bbb 11   LTP   Long to Packed

Note that the mnemonic of an instruction is not changed by the type of base register it uses, as that is implicit in the location of the variable it references.


The fiftieth through sixty-first lines show the format of additional multiple-register load and store instructions, which are used to save and restore the registers at the beginning and end of subroutines.

These instructions have the opcodes:

01 0 100 0000010000  u0                 LMSS     Load Multiple Superscalar
01 0 100 0000010000  u1                 STMSS    Store Multiple Superscalar

01 0 100 0000010001  0000               LMV      Load Multiple Vector
01 0 100 0000010001  0001               STMV     Store Multiple Vector

01 0 100 0000010001  001000             LML    Load Multiple Long
01 0 100 0000010001  001001             STML   Store Multiple Long
01 0 100 0000010001  001010             LMQ    Load Multiple Quad
01 0 100 0000010001  001011             STMQ   Store Multiple Quad
01 0 100 0000010001  001100             LMB    Load Multiple Base
01 0 100 0000010001  001101             STMB   Store Multiple Base

01 0 100 001 rrrrrrr u0 rrrrrr 0000     LMSS     Load Multiple Superscalar
01 0 100 001 rrrrrrr u0 rrrrrr 0001     STMSS    Store Multiple Superscalar

01 0 100 0000010010  0                  LMV      Load Multiple Vector
01 0 100 0000010010  1                  STMV     Store Multiple Vector

01 0 100 0000010011  0 rrrrr rrrrr 00   LML    Load Multiple Long
01 0 100 0000010011  0 rrrrr rrrrr 01   STML   Store Multiple Long
01 0 100 0000010011  0 rrrrr rrrrr 10   LMQ    Load Multiple Quad
01 0 100 0000010011  0 rrrrr rrrrr 11   STMQ   Store Multiple Quad
01 0 100 0000010011  1 rrrrr rrrrr 00   LMB    Load Multiple Base
01 0 100 0000010011  1 rrrrr rrrrr 01   STMB   Store Multiple Base

01 0 100 0000010100  0000 rrrr rrrr 0   LMSV   Load Multiple Short Vector
01 0 100 0000010100  0000 rrrr rrrr 1   STMSV  Store Multiple Short Vector

01 0 100 0000010100  0001000            LMSB    Load Multiple Short Base
01 0 100 0000010100  0001001            STMSB   Store Multiple Short Base            
01 0 100 0000010100  0001010            LMLB    Load Multiple Long Base
01 0 100 0000010100  0001011            STMLB   Store Multiple Long Base
01 0 100 0000010100  0001100            LMEB    Load Multiple Extended Base
01 0 100 0000010100  0001101            STMEB   Store Multiple Extended Base
01 0 100 0000010100  0001110            LMCB    Load Multiple Code Base
01 0 100 0000010100  0001111            STMCB   Store Multiple Code Base

01 0 100 0001 rrrrrr  0 rrrrrr bbb 00   LMSS     Load Multiple Superscalar
01 0 100 0001 rrrrrr  0 rrrrrr bbb 01   STMSS    Store Multiple Superscalar

01 0 100 00001 rrrrr  0 rrrrr 0 bbb 00  LML    Load Multiple Long
01 0 100 00001 rrrrr  0 rrrrr 0 bbb 01  STML   Store Multiple Long  
01 0 100 00001 rrrrr  0 rrrrr 0 bbb 10  LMQ    Load Multiple Quad  
01 0 100 00001 rrrrr  0 rrrrr 0 bbb 11  STMQ   Store Multiple Quad  
01 0 100 00001 rrrrr  0 rrrrr 1 bbb 01  LMB    Load Multiple Base  
01 0 100 00001 rrrrr  0 rrrrr 1 bbb 01  STMB   Store Multiple Base

01 0 100 010000 rrrr  rrrr 000 bbb 00   LMSV   Load Multiple Short Vector
01 0 100 010000 rrrr  rrrr 000 bbb 01   STMSV  Store Multiple Short Vector

01 0 100 0000010101  0 rrr rrr bbb 00   LMSB    Load Multiple Short Base
01 0 100 0000010100  0 rrr rrr bbb 01   STMSB   Store Multiple Short Base            
01 0 100 0000010100  0 rrr rrr bbb 10   LMLB    Load Multiple Long Base
01 0 100 0000010100  0 rrr rrr bbb 11   STMLB   Store Multiple Long Base
01 0 100 0000010100  1 rrr rrr bbb 00   LMEB    Load Multiple Extended Base
01 0 100 0000010100  1 rrr rrr bbb 01   STMEB   Store Multiple Extended Base
01 0 100 0000010100  1 rrr rrr bbb 10   LMCB    Load Multiple Code Base
01 0 100 0000010100  1 rrr rrr bbb 11   STMCB   Store Multiple Code Base

The sixty-second line shows the format of those conditional jump instructions that use the extended page base registers.

Their opcodes are:

01 0 100 0000010101  0000 000 bbb 00  NOP  No Operation
01 0 100 0000010101  0001 000 bbb 00  JLT  Jump if Less Than
01 0 100 0000010101  0010 000 bbb 00  JEQ  Jump if Equal
01 0 100 0000010101  0011 000 bbb 00  JLE  Jump if Less than or Equal
01 0 100 0000010101  0100 000 bbb 00  JGT  Jump if Greater Than
01 0 100 0000010101  0101 000 bbb 00  JNE  Jump if Not Equal
01 0 100 0000010101  0110 000 bbb 00  JGE  Jump if Greater than or Equal
01 0 100 0000010101  0111 000 bbb 00  JMP  Jump

01 0 100 0000010101  1000 000 bbb 00  JV   Jump if oVerflow
01 0 100 0000010101  1001 000 bbb 00  JNV  Jump if No oVerflow
01 0 100 0000010101  1010 000 bbb 00  JC   Jump if Carry
01 0 100 0000010101  1011 000 bbb 00  JNC  Jump if No Carry

The sixty-third line shows the format of the subroutine jump instructions that use the extended page base registers.

Their opcodes are:

01 0 100 0000010101  0000 000 bbb 01     JSR      Jump to Subroutine
01 0 100 0000010101  0000 000 bbb 10     JSRLR    Jump to Subroutine Long Return
01 0 100 0000010101  0000 000 bbb 11     JSRYR    Jump to Subroutine Extended Return

The sixty-fourth line shows the format of the 48-bit instruction which provides a form of 32-bit instructions which permit predicated execution. 16-bit instructions can also be wrapped with this instruction format, with the last 16 bits of the instruction being ignored.

The prefix has the form 01 0 100 0110 s fff 000.


The sixty-fifth and sixty-sixth lines show the format of instructions designed to facilitate rapid superscalar processing without requiring extensive support of out-of-order execution.

This is achieved by the following measures:

These instructions are provided for operations that, by their nature, can take advantage of such facilities for static scheduling of superscalar operations, such as would be performed on Digital Signal Processor devices.

They will be described in detail on a later page.

The 64-bit instructions

The sixty-seventh line shows the format of the first type of 64-bit instruction we encounter. Here, a 48-bit instruction is given an instruction prefix to make it a predicated instruction.

The opcode of the instruction prefix is 01 0 11 0000 s fff 000. The three flag bits indicate which of the seven flags will determine if the instruction is executed, and the s bit indicates, if it is 0, that the instruction will execute if the flag bit is cleared, and if it is 1, that the instruction will excute if the flag bit is set.


The sixty-eighth line shows the format of additional immediate operate instructions which have 32-bit immediate operands. As there are a large number of these instructions, they will be described on a later page, but they will all have opcodes starting with 01 c 11 0000 oooo 001.


The sixty-ninth line shows the format of string instructions which use the long page base registers. These instructions, unlike the 48-bit instructions which use the short page base registers, may be indexed.

Since these instructions do not have a destination register field, but their index register field is still only three bits long rather than five bits long, they use general registers 1 through 7 as index registers.

These instructions have the opcodes:

01 c 11 00100 xxx yyy  llllllll 00   T    Translate
01 c 11 00100 xxx yyy  llllllll 01   CC   Compare Character
01 c 11 00100 xxx yyy  llllllll 10   MVC  Move Character
01 c 11 00100 xxx yyy  llllllll 11   TT   Translate and Test
01 c 11 00101 xxx yyy  llllllll 00   P    Pack
01 c 11 00101 xxx yyy  llllllll 01   UP   Unpack
01 c 11 00101 xxx yyy  llllllll 10   E    Edit
01 c 11 00101 xxx yyy  llllllll 11   EM   Edit and Mark

The seventieth line shows the format of string instructions using the extended page base registers. These instructions do not provide indexing.

These instructions have the opcodes:

01 c 11 10 bbb 00 aaaa  ...  0 bbb llllllll   T    Translate
01 c 11 10 bbb 00 aaaa  ...  1 bbb llllllll   CC   Compare Character
01 c 11 10 bbb 01 aaaa  ...  0 bbb llllllll   MVC  Move Character
01 c 11 10 bbb 01 aaaa  ...  1 bbb llllllll   TT   Translate and Test
01 c 11 10 bbb 10 aaaa  ...  0 bbb llllllll   P    Pack
01 c 11 10 bbb 10 aaaa  ...  1 bbb llllllll   UP   Unpack
01 c 11 10 bbb 11 aaaa  ...  0 bbb llllllll   E    Edit
01 c 11 10 bbb 11 aaaa  ...  1 bbb llllllll   EM   Edit and Mark

The seventy-first line shows the format of packed decimal instructions that use the long page base registers. These instructions, unlike the 48-bit instructions which use the short page base registers, may be indexed.

These instructions have the opcodes:

01 c 11 00110 xxx yyy  llllllll 01   CP   Compare Packed
01 c 11 00110 xxx yyy  llllllll 10   MVP  Move Packed

01 c 11 00111 xxx yyy  llllllll 00   AP   Add Packed
01 c 11 00111 xxx yyy  llllllll 01   SP   Subtract Packed
01 c 11 00111 xxx yyy  llllllll 10   MP   Multiply Packed
01 c 11 00111 xxx yyy  llllllll 11   DP   Divide Packed

The seventy-second line shows the format of packed decimal instructions using the extended page base registers. These instructions do not provide indexing.

These instructions have the opcodes:

01 c 11 11 bbb 00 aaaa  ...  1 bbb llllllll   CP   Compare Packed
01 c 11 11 bbb 01 aaaa  ...  0 bbb llllllll   MVP  Move Packed

01 c 11 11 bbb 10 aaaa  ...  0 bbb llllllll   AP   Add Packed
01 c 11 11 bbb 10 aaaa  ...  1 bbb llllllll   SP   Subtract Packed
01 c 11 11 bbb 11 aaaa  ...  0 bbb llllllll   MP   Multiply Packed
01 c 11 11 bbb 11 aaaa  ...  1 bbb llllllll   DP   Divide Packed

The seventy-third line shows the format of a three-address form of the Translate instruction. In this format, the first address constant indicates the destination argument, the second address constant indicates the operand argument, which is the translate table, and the third address constant indicates the source argument. In this way, a translate can be performed on a string while retaining the original version of the string without the need for making an extra copy first before starting.

This instruction has the opcode 01 c 11 010.


The seventy-fourth line shows the format of the form of the long vector memory-reference instructions that uses the extended page base registers.

The opcodes of these instructions begin with 01 0 11 011, and they will be described on a later page.

The seventy-fifth line shows the format of additional memory-reference instructions using the extended page base registers, and as with other instructions involving the full set of memory-reference instructions, it will be described on a later page.


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