The instruction formats for this architecture are as shown below:
However, in each aligned 256-bit block of instruction code, the last instruction may not be one with the E bit set. 32-bit instructions starting with 01 are instead interpreted as follows:
The last 16 bits of these instructions are in the form of a 16-bit register-to-register instruction. This further reduces the overhead cost imposed by the feature for which this category of instruction is provided.
And that feature is fine-grained control over branching.
The 14-bit field extending from bits 2 to 15 of the 32-bit instruction word (bits numbered 0 through 31 from left to right) is divided into two-bit fields, each one corresponding to one of the 32-bit instructions in the current block (not the next one).
The possible values of each two-bit subfield in this area are as follows:
00: may be the destination of a jump (normal code) 01: local branches only (prefixed instruction) 10: jump to the odd half-word is allowed (pair of 16-bit instructions) 11: may not be a branch target (immediate data)
In parentheses after the description of the restriction imposed by each value is the type of item occupying that 32-bit slot to which that restriction is applicable.
Thus, this field could be used to describe the contents of an instruction block, while at the same time imposing only the minimal restriction on branching of prohibiting those types of branches which do not make sense for the particular type of item present.
In the case of a prefixed instruction, local branches, that is, conditional jump instructions as opposed to subroutine call instructions which also are in the program-counter relative addressing mode, are the only ones which do not clear the prefix registers, as a security feature.
It is not, however, required that this field correctly describe the contents of the instruction block; it can instead be used to prohibit branching to any location to which branching is not intended to take place.
If the final 32-bit instruction slot in a 256-bit instruction block does not begin with 01, whether or not branching into that instruction block is permitted will depend on security status settings for a given program. In general, branches from outside code will always be restricted if they are allowed at all; branches internal to code with a single owner may also be restricted to those that make sense, or to those specifically allowed, to protect programs against such things as problems caused by invalid input data, or they may not be limited in order to avoid the overhead of indicating which branches are permitted.
Note, however, that the other type of 32-bit instruction that has as its last 16 bits a 16-bit register-to-register instruction, contains an eight-bit mask, the bits of which indicate that the corresponding 32-bit slot in the next 256-bit instruction block contains two 16-bit register-to-register instructions. If the last bit of that mask is set, then the instruction code in the last 32-bit slot will not receieve special treatment if it begins with 01.
Avoiding the use of the final slot in this way is, therefore, necessary if it is intended to construct machine code which makes use of this feature to aggressively prevent invalid branches within the code. If this level of security is not required, and there will not be branches into the block that will lead to unexpected results due to the instructions in the final 32-bit unit being misinterpreted as a single instruction, then it can be used for a pair of 16-bit instructions.
Note that one of the formats for the final instruction block is labelled "Special Block Indicator".
This is intended to provide a means for dealing with one possible situation involving instructions with supplementary prefix bits that has so far not been accounted for. Since the prefix registers must be set prior to the 256-bit instruction block in which their contents are used, the number and variety of prefixed instructions in any one block is limited. If it is desired to have many diverse prefixed instructions in close proximity in the sequence of code, padding with no-operation instructions would become necessary. A feature has been added to avoid this situation.
The bit marked R is used to indicate that a code block is a "Recipient" block, and the bit marked D is used to indicate that a code block is a "Donor" block. For each recipient block, the block immediately following must be a donor block. A block may be both a recipient and a donor.
In a recipient block, if there are instructions with the E bit set, the prefix bits for those instructions are not taken from the prefix registers. Instead, they are to be found at the beginning of the following instruction block.
The prefix bits are coded as shown in the diagram below:
Thus, the sequence of prefix bits will be a multiple of 8 bits. Also note that 15-bit prefixes beginning with 000 and 30-bit prefixes beginning with 000000 are not available by this means; the leading zeroes are instead used to indicate the more common 12-bit and 24-bit prefix sizes (those sizes being more common as they require less effort to set up by the normal means of using the prefix registers).
The space taken at the beginning of the block for prefix bits must be a multiple of 32 bits, and so 8, 16, or 24 bits at the end of the last 32 bits so taken may be unused.
If the recipient block also contains instructions which call for immediate operands (other than the 8-bit and 16-bit ones that are contained within a 32-bit instruction), these operand values are in the 32-bit instruction slots following the ones used for prefix bits. This is a natural result of the fact that immediate operands are found at a later stage of instruction decoding than the request for prefix bits (and, indeed, prefix bits to an instruction could potentially even change whether it takes an immediate operand, although it is intended to design the instruction set to avoid this case).
Note that the individual prefix bit items vary in length, and the length they occupy, eight, sixteen, or thirty-two bits, is indicated by their first bits. Thus, serialized instruction decoding, as is required on CISC architectures with variable-length instructions, is needed here, but only for those instruction sequences with a high proportion of longer instructions which require it.
In addition to allowing the sequence of instructions to be more general, placing the information about prefix bits at the beginning of the block following the block with prefixed instructions, instead of in instructions in the preceding block, makes it easier for those prefixed instructions to be branch targets with correct results.
Further to this end, the H and P bits are present in the Special Block Indicator instruction. If either of them is set, an additional instruction slot is reserved in the following block, prior to both the sequence of prefix bits, if called for, and to immediate values, if present.
If the H bit is set, the first eight bits in that instruction slot indicate which instruction slots in the current block contain a pair of 16-bit instructions.
If the P bit is set, each three bits in the last 24 bits of that instruction slot indicate an instruction predicate for one of the instructions in the current block. (The last three of those bits, of course, are ignored, since a Special Block Indicator item, although it fills an instruction slot, does'nt perform any operations, it only helps to describe the instructions found in the other instruction slots of the block.)
The B bit, if it is set, replaces the fourteen branch control bits in the earlier part of the instruction item with eight bits. Each of these bits corresponds to an instruction slot in the previous block.
Instead of using the R (Recipient), H (Halfword instruction), or P (Predicate) bit to change how instructions are prefixed, so that the information is in the next block, the B bit, when set, uses this eight-bit field to indicate where the instructions are that affect how the current block is decoded.
Instructions that set prefix bits, or which directly prepend a prefix to instructions in the next block, are indicated in this way. If a branch takes place to any instruction in the current block, those instructions in the previous block would also be executed in order that the current block would be decoded properly.
Instructions that call for immediate values would also be indicated; those would not be executed, but the number of instruction slots they call for to be used for immediate values would be noted.
Note that the B bit can still be set when one or more of the R, H, and P bits are set; if the R bit is set, the preceding block can still contain instructions to set the prefix registers, as their values need not be used in the immediately following instruction block. Normally, the eight-bit field indicating items relevant to decoding would not indicate those instructions in that case, but if they were indicated, they are to be ignored in that case.
If either the H or P bits are set, however, the previous block is not to contain the instructions which also indicate paired 16-bit instructions or predication which correspond to which of those bits are set. (That is, if the P bit is set, but not the H bit, paired 16-bit instructions can still be indicated in the preceding block, and, similarly, if the H bit is set, but not the P bit, predication can still be indicated in the preceding block.) If a double indication of halfword instructions or predication is present, the program will trap, and this trap should normally be treated as an unrecoverable failure of the program.