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The Concertina III Architecture

This is an attempt to construct a computer architecture offering a wide selection of instructions, and features to promote high-speed decoding of instructions, which still offers a relatively simple instruction format.

The basic instruction set provides for instructions that may be 16, 32, 48, 64, or 80 bits long. In some ways, it resembles that of a well-known mainframe computer from a major manufacturer, but there are significant differences: 48-bit instructions are a smaller part of the opcode space, and longer instructions are provided for.

Also, as is the case in some RISC architectures, there is a C bit in many instructions, to make setting the condition codes optional, so that instructions can be placed between an instruction setting the condition codes and a conditional branch that depends on them. Usually, allowing the condition codes to be changed is the only effect of setting the C bit on an instruction, but there is one important exception to this, the progressive long vector instructions.

The computer may operate in four modes.

Mode 0: Basic Mode

In this mode, instructions are conventionally organized, one instruction following the previous one, each instruction having the length indicated by its first few bits.

The first few bits of an instruction indicate its length as follows:

011110 - 64 bits
011111 - 80 bits
011xx  - 48 bits
0xx    - 16 bits
1      - 32 bits

where xx indicates a pair of bits where it is not the case that both of them are 1.

Mode 1: Fast Decode Mode

Here, each 256-bit block of instruction code begins with a 16-bit header in this form:

The first 15 bits of the header correspond to the remaining fifteen 16-bit pieces of the block, and when one of its bits is set to 1, this indicates that an instruction begins there.

The sixteenth bit of the header is a 1 if the last instruction within the block is complete within the block.

The actual length of the instruction is indicated by the first few bits of the instruction as in Mode 0; any additional 16-bit halfwords between halfwords corresponding to bits set in the decode part of the header are simply unused. They will be skipped over in normal execution, but the return address of a subroutine jump instruction will point into them, and must be adjusted by the subroutine itself; this allows the return address to point to data to be passed to the subroutine for which space has been reserved in the instruction stream.

Mode 2: CISC/VLIW Mode

In this mode, each 256-bit block of instruction code begins with a 32-bit header in this form:

The first 16 bits are similar to the headers in Mode 1, except that the first bit, being unused, must be zero.

The remaining 16 bits consist of a zero, 14 bits each corresponding to one of the remaining 16 bit halfwords available for instructions in the block, and another zero. These bits may only be set where they correspond to a bit that is set in the first half of the header, and they indicate the beginning of a block of instructions within which there are no dependencies, so that all the instructions within that block may be executed in parallel.

Mode 3: RISC/VLIW Mode

In this mode, only 32-bit instructions are used. Instead of always being a 1, the first bit of the instruction is used to group instructions into short sequences in which all the instructions may be executed in parallel. The first bit of the first instruction in each such group is 1, and that of all other instructions within that group is 0.

The 32-bit instructions in themselves form a complete computer instruction set, even if they exclude some extra features.

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