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Basic Opcodes

For reference, as we look at the opcodes for the register-to-register and memory-reference instructions, here is the diagram of the instruction formats of this architecture that we saw on the preceding page once again:

The opcodes for register-to-register, memory-reference, three-address register, and enlarged file register-to-register instructions are shown in the table below.

The format of the 16-bit register-to-register instructions is shown in Line 1 of the diagram; such instructions also appear on lines 3, 4, 5, 6, 7, 8, 9, 10 and 18 of the diagram.

The basic format of normal memory-reference instructions is shown on line 12 of the diagram. Short address memory-reference instructions, as shown in line 13, have three additional opcode bits; the opcode is shifted right in that case, so that some opcode space is available to indicate enlarged file memory-reference instructions and multiple-register instructions.

Enlarged register file memory reference instructions have their format shown on line 15 of the diagram, the format of three-address register-to-register instructions is shown on line 15 of the diagram, and the format of enlarged register file register-to-register instructions is shown on line 36 of the diagram.

The opcodes are shown below in the context of the octal representation of either the first 16 bits of the instruction, or all 32 bits of the instruction divided into two parts. Where one octal digit, in addition to including bits either belonging to the opcode or with a fixed value, also spans bits with another function, the value of the octal digit shown is that for when those bits with another function (such as the C bit, indicating an instruction is allowed to change the condition code) are all zero.

An octal digit only spanning bits that are variable is shown as an x.

16-bit         Memory       Memory       Enlarged       Three-Address    Enlarged File
Register to    Reference    Reference    File Memory    Register to      Register to
Register       (long base)  (short base) Reference      Register         Register
------         -----        -----        -----          -------------    -------------
1400xx         000xxx       0000xx       020x0x         140000 000xxx    140066 0xxxxx     SWB    Swap Byte
1401xx         001xxx       0001xx       020x1x         140000 001xxx    140166 0xxxxx     CB     Compare Byte
1402xx         002xxx       0002xx       020x2x         140000 002xxx    140266 0xxxxx     LB     Load Byte
               003xxx       0003xx       020x3x                                            STB    Store Byte
1404xx         004xxx       0004xx       022x0x         140000 004xxx    140466 0xxxxx     AB     Add Byte
1405xx         005xxx       0005xx       022x1x         140000 005xxx    140566 0xxxxx     SB     Subtract Byte
(see conditional jump instructions)
(see conditional jump instructions)
                                                            
1410xx         010xxx       0010xx       024x0x         140000 010xxx    141066 0xxxxx     IB     Insert Byte
1411xx         011xxx       0011xx       024x1x         140000 011xxx    141166 0xxxxx     UCB    Unsigned Compare Byte
1412xx         012xxx       0012xx       024x2x         140000 012xxx    141266 0xxxxx     ULB    Unsigned Load Byte
1413xx         013xxx       0013xx       024x3x         140000 013xxx    141366 0xxxxx     XB     XOR Byte
1414xx         014xxx       0014xx       026x0x         140000 014xxx    141466 0xxxxx     NB     AND Byte
1415xx         015xxx       0015xx       026x1x         140000 015xxx    141566 0xxxxx     OB     OR Byte
(see jump to subroutine instructions)                                              
               017xxx       0017xx       026x3x                                            STGB   Store if Greater Byte
                                                            
1420xx         020xxx       0020xx       030x0x         140000 020xxx    142066 0xxxxx     SWH    Swap Halfword
1421xx         021xxx       0021xx       030x1x         140000 021xxx    142166 0xxxxx     CH     Compare Halfword
1422xx         022xxx       0022xx       030x2x         140000 022xxx    142266 0xxxxx     LH     Load Halfword
               023xxx       0023xx       030x3x                                            STH    Store Halfword
1424xx         024xxx       0024xx       032x0x         140000 024xxx    142466 0xxxxx     AH     Add Halfword
1425xx         025xxx       0025xx       032x1x         140000 025xxx    142566 0xxxxx     SH     Subtract Halfword
1426xx         026xxx       0026xx       032x2x         140000 026xxx    142666 0xxxxx     MH     Multiply Halfword
1427xx         027xxx       0027xx       032x3x         140000 027xxx    142766 0xxxxx     DH     Divide Halfword
                                                            
1430xx         030xxx       0030xx       034x0x         140000 030xxx    143066 0xxxxx     IH     Insert Halfword
1431xx         031xxx       0031xx       034x1x         140000 031xxx    143166 0xxxxx     UCH    Unsigned Compare Halfword
1432xx         032xxx       0032xx       034x2x         140000 032xxx    143266 0xxxxx     ULH    Unsigned Load Halfword
1433xx         033xxx       0033xx       034x3x         140000 033xxx    143366 0xxxxx     XH     XOR Halfword
1434xx         034xxx       0034xx       036x0x         140000 034xxx    143466 0xxxxx     NH     AND Halfword
1435xx         035xxx       0035xx       036x1x         140000 035xxx    143566 0xxxxx     OH     OR Halfword
1436xx         036xxx       0036xx       036x2x         140000 036xxx    143666 0xxxxx     MEH    Multiply Extensibly Halfword
1437xx         037xxx       0037xx       036x3x         140000 037xxx    143766 0xxxxx     DEH    Divide Extensibly Halfword
                                                            
1500xx         040xxx       0040xx       060x0x         150000 000xxx    150066 0xxxxx     SW     Swap
1501xx         041xxx       0041xx       060x1x         150000 001xxx    150166 0xxxxx     C      Compare
1502xx         042xxx       0042xx       060x2x         150000 002xxx    150266 0xxxxx     L      Load
               043xxx       0043xx       060x3x                                            ST     Store
1504xx         044xxx       0044xx       062x0x         150000 004xxx    150466 0xxxxx     A      Add
1505xx         045xxx       0045xx       062x1x         150000 005xxx    150566 0xxxxx     S      Subtract
1506xx         046xxx       0046xx       062x2x         150000 006xxx    150666 0xxxxx     M      Multiply
1507xx         047xxx       0047xx       062x3x         150000 007xxx    150766 0xxxxx     D      Divide
                            
1510xx         050xxx       0050xx       064x0x         150000 010xxx    151066 0xxxxx     I      Insert                                               
1511xx         051xxx       0051xx       064x1x         150000 011xxx    151166 0xxxxx     UC     Unsigned Compare
1512xx         052xxx       0052xx       064x2x         150000 012xxx    151266 0xxxxx     UL     Unsigned Load                                               
1513xx         053xxx       0053xx       064x3x         150000 013xxx    151366 0xxxxx     X      XOR
1514xx         054xxx       0054xx       066x0x         150000 014xxx    151466 0xxxxx     N      AND
1515xx         055xxx       0055xx       066x1x         150000 015xxx    151566 0xxxxx     O      OR
1516xx         056xxx       0056xx       066x2x         150000 016xxx    151666 0xxxxx     ME     Multiply Extensibly
1517xx         057xxx       0057xx       066x3x         150000 017xxx    151766 0xxxxx     DE     Divide Extensibly
                                                            
1520xx         060xxx       0060xx       070x0x         150000 020xxx    152066 0xxxxx     SWL    Swap Long
1521xx         061xxx       0061xx       070x1x         150000 021xxx    152166 0xxxxx     CL     Compare Long
1522xx         062xxx       0062xx       070x2x         150000 022xxx    152266 0xxxxx     LL     Load Long
               063xxx       0063xx       070x3x                                            STL    Store Long
1524xx         064xxx       0064xx       072x0x         150000 024xxx    152466 0xxxxx     AL     Add Long
1525xx         065xxx       0065xx       072x1x         150000 025xxx    152566 0xxxxx     SL     Subtract Long
1526xx         066xxx       0066xx       072x2x         150000 026xxx    152666 0xxxxx     ML     Multiply Long
1527xx         067xxx       0067xx       072x3x         150000 027xxx    152766 0xxxxx     DL     Divide Long
                            
1530xx         070xxx       0070xx       074x0x         150000 030xxx    153066 0xxxxx     LA     Load Address                                               
1531xx         071xxx       0071xx       074x1x         150000 031xxx    153166 0xxxxx     UCL    Unsigned Compare Long
1532xx         072xxx       0072xx       074x2x         150000 032xxx    153266 0xxxxx     LB     Load Base                                              
1533xx         073xxx       0073xx       074x3x         150000 033xxx    153366 0xxxxx     XL     XOR Long
1534xx         074xxx       0074xx       076x0x         150000 034xxx    153466 0xxxxx     NL     AND Long
1535xx         075xxx       0075xx       076x1x         150000 035xxx    153566 0xxxxx     OL     OR Long
1536xx         076xxx       0076xx       076x2x         150000 036xxx    153666 0xxxxx     MEL    Multiply Extensibly Long
1537xx         077xxx       0077xx       076x3x         150000 037xxx    153766 0xxxxx     DEL    Divide Extensibly Long
                                                            
1600xx         100xxx       0100xx       120x0x         160000 000xxx    160066 0xxxxx     SWM    Swap Medium
1601xx         101xxx       0101xx       120x1x         160000 001xxx    160166 0xxxxx     CM     Compare Medium
1602xx         102xxx       0102xx       120x2x         160000 002xxx    160266 0xxxxx     LM     Load Medium
               103xxx       0103xx       120x3x                                            STM    Store Medium
1604xx         104xxx       0104xx       122x0x         160000 004xxx    160466 0xxxxx     AM     Add Medium
1605xx         105xxx       0105xx       122x1x         160000 005xxx    160566 0xxxxx     SM     Subtract Medium
1606xx         106xxx       0106xx       122x2x         160000 006xxx    160666 0xxxxx     MM     Multiply Medium
1607xx         107xxx       0107xx       122x3x         160000 007xxx    160766 0xxxxx     DM     Divide Medium
                                                            
1610xx         110xxx       0110xx       124x0x         160000 010xxx    161066 0xxxxx     SWF    Swap Floating
1611xx         111xxx       0111xx       124x1x         160000 011xxx    161166 0xxxxx     CF     Compare Floating
1612xx         112xxx       0112xx       124x2x         160000 012xxx    161266 0xxxxx     LF     Load Floating
               113xxx       0113xx       124x3x                                            STF    Store Floating
1614xx         114xxx       0114xx       126x0x         160000 014xxx    161466 0xxxxx     AF     Add Floating
1615xx         115xxx       0115xx       126x1x         160000 015xxx    161566 0xxxxx     SF     Subtract Floating
1616xx         116xxx       0116xx       126x2x         160000 016xxx    161666 0xxxxx     MF     Multiply Floating
1617xx         117xxx       0117xx       126x3x         160000 017xxx    161766 0xxxxx     DF     Divide Floating
                                                            
1620xx         120xxx       0120xx       130x0x         160000 020xxx    162066 0xxxxx     SWD    Swap Double
1621xx         121xxx       0121xx       130x1x         160000 021xxx    162166 0xxxxx     CD     Compare Double
1622xx         122xxx       0122xx       130x2x         160000 022xxx    162266 0xxxxx     LD     Load Double
               123xxx       0123xx       130x3x                                            STD    Store Double
1624xx         124xxx       0124xx       132x0x         160000 024xxx    162466 0xxxxx     AD     Add Double
1625xx         125xxx       0125xx       132x1x         160000 025xxx    162566 0xxxxx     SD     Subtract Double
1626xx         126xxx       0126xx       132x2x         160000 026xxx    162666 0xxxxx     MD     Multiply Double
1627xx         127xxx       0127xx       132x3x         160000 027xxx    162766 0xxxxx     DD     Divide Double
                                                            
1630xx         130xxx       0130xx       134x0x         160000 030xxx    163066 0xxxxx     SWQ    Swap Quad
1631xx         131xxx       0131xx       134x1x         160000 031xxx    163166 0xxxxx     CQ     Compare Quad
1632xx         132xxx       0132xx       134x2x         160000 032xxx    163266 0xxxxx     LQ     Load Quad
               132xxx       0132xx       134x3x                                            STQ    Store Quad
1634xx         134xxx       0134xx       136x0x         160000 034xxx    163466 0xxxxx     AQ     Add Quad
1635xx         135xxx       0135xx       136x1x         160000 035xxx    163566 0xxxxx     SQ     Subtract Quad
1636xx         136xxx       0136xx       136x2x         160000 036xxx    163666 0xxxxx     MQ     Multiply Quad
1637xx         137xxx       0137xx       136x3x         160000 037xxx    163766 0xxxxx     DQ     Divide Quad

The types on which these instructins act are:

Byte       8-bit two's complement integer
Halfword   16-bit two's complement integer
(Word)     32-bit two's complement integer
Long       64-bit two's complement integer

Medium     48-bit floating-point
Floating   32-bit floating-point
Double     64-bit floating-point
Quad       128-bit floating-point

The floating-point formats are described in more detailed below. They are patterned after those of IEEE 754, as used by many other computers, and are illustrated in the diagram below:



In addition to the standard 32-bit and 64-bit types specified by IEEE 754, a similar type occupying 48 bits is defined. The size of the exponent field is chosen to be the minimum that allows numbers from 10^-99 to 10^99 to be represented, and with that exponent field, 11 digits of precision are provided. Thus, this format matches the precision provided by many pocket calculators, as well as used in mathematical tables and mechanical calculators; thus, historically, it appears to be a good fit to what many scientific problems require.


The extended-precision format of floating-point number may be used in the registers for floating-point numbers of all precisions.

Thus, when a register-to-register operation involving a shorter precision is performed, some bits of the register are ignored when operands are taken, but all bits are filled to provide a valid extended-precision number with the proper value when results are returned.

This has the positive consequence that denormals do not require any additional overhead. It also means that single-precision, double-precision, and intermediate-precision numbers, in internal form, have a slightly greater numeric range than they do in external form.

This means that some computations may continue, and produce a correct result, which would otherwise fail if the numbers were kept in external form all the way through. However, this still tends to be viewed as a drawback, as it means that computations are less consistent in their results. Also, this means that instructions to store floating-point numbers other than extended precision floating point numbers may fail with an overflow or underflow error.

Therefore, a mode setting exists to determine if floating-point numbers will be converted to internal form when they are placed in registers, or stored there in the external form for greater consistency at the cost of somewhat slower speed.


The operations performed by the instructions shown in the table above are:

Swap: The contents of the source and destination are exchanged. In the case of Swap Byte, Swap Halfword, and Swap, sign extension is performed in the register that is the destination operand.

Compare: This instruction sets the condition codes as though the source operand was subtracted from the destination operand, except that an idealized subtraction is performed, in which the destination register is enlarged so that overflow cannot occur. Thus, in Compare Long, if the source operand is the largest possible 64-bit integer, and the destination operand is the smallest possible 64-bit integer, the largest possible negative value, the condition codes will be set for a negative result, correctly indicating the destination is less than the source.

Load: This instruction places the contents of the source operand in the destination register. In the case of Load Byte, Load Halfword, and Load, the value of the source operand is then sign extended to fill the destination register.

Store: This instruction places the contents of the destination register in the source operand in memory, truncated as required to fit.

Add: This instruction places the sum of the values in the source operand and the destination register (or the operand register, if three-address) in the destination register.

Subtract: This instruction, if two-address, subtracts the value of the source operand from the value in the destination register, and places the result in the destination register. If it is three-address, it subtracts the value in the source operand from the value of the operand register, and places the result in the destination register.

Multiply: This instruction places the product of the values in the source operand and the destination register (or the operand register, if three-address) in the destination register.

Divide: This instruction, if two-address, divides the value in the destination register by the value of the source operand, and places the quotient in the destination register. If it is three-address, it divides the value in the operand register by the value of the source operand, and places the quotient in the destination register.

Insert: This instruction places the contents of the source operand in the rightmost bits of the destination register, leaving bits to the left of the length of the source operand remaining unaffected.

Unsigned Compare: This instruction sets the condition codes in a manner corresponding to an idealized subtraction of the destination from the source where both values are treated as positive binary numbers rather than any values being considered to correspond to negative numbers using two's complement notation.

Unsigned Load: This instruction loads the rightmost bits of the destination register with the value of the source operand, clearing all the bits to the left of the length of the source opreand.

XOR: This instruction performs an Exclusive OR operation between the source operand and the destination register. In the case of XOR Byte, XOR Halfword, and XOR, bits to the left of the length of the source operand are unaffected.

AND: This instruction performs a Logical AND operation between the source operand and the destination register. In the case of AND Byte, AND Halfword, and AND, bits to the left of the length of the source operand are unaffected.

OR: This instruction performs a Logical OR operation between the source operand and the destination register. In the case of OR Byte, OR Halfword, and OR, bits to the left of the length of the source operand are unaffected.

Store if Greater: This instruction stores the contents of the destination register in the source operand location if the value in the destination register, considered as an unsigned integer, is greater than the value of the source operand. This instruction executes as an atomic operation.

Load Address: This instruction stores the effective address of the instruction, the location from which a source operand would be taken, in the short base register indicated by the destination register field. In the case of an Extended Regster File memory-reference instruction, values 8 through 15 in that field indicate the long base registers.

Load Base: This instruction stores the value of the source operand in the short base register indicated by the destination register field. In the case of an Extended Regster File memory-reference instruction, values 8 through 15 in that field indicate the long base registers.

Multiply Extensibly: This instruction multiplies the value of the source operand by the contents of the destination register, storing the product in the destination register, with sign extension if required. Considering the source operand to be the multiplier, the multiplicand is the rightmost portion of the destination register corresponding to the source operand in length, while the product is allowed to occupy the rightmost portion of the destination register having twice that length. In the case of Multiply Extensibly Long, the destination register must be an odd-numbered register, and the least significant half of the product is placed in that register, with the most significant half of the product being placed in the register preceding the destination register.

Divide Extensibly: This instruction divides the contents of the destination register by the value of the source operand, placing the quotient in the destination register and the remainder in the register following. The remainder has the same length as the source operand, which length is the one indicated by the type of the instruction. The dividend in the destination register and the quotient in the destination register both have twice the length of the source operand, and the quotient is sign-extended if necessary. In the case of Divide Extensibly Long, the destination register must be an even-numbered register, and that register and the one following are used to provide the dividend and to store the quotient. The remainder occupies only one register, in this case not the next register from the destination register, but the one after, so that the results of this instruction occupy three consecutive registers.


In addition, this area of the opcode space is also used for the Conditional Jump and Jump to Subroutine instructions:

Memory       Memory       Enlarged
Reference    Reference    File Memory
(long base)  (short base) Reference
-----        -----        -----
0061xx       00061x       02206x    JL      Jump if Low
0062xx       00062x       02212x    JE      Jump if Equal
0063xx       00063x       02216x    JLE     Jump if Low or Equal
0064xx       00064x       02222x    JH      Jump if High
0065xx       00065x       02226x    JNE     Jump if Not Equal
0066xx       00066x       02232x    JHE     Jump if High or Equal
0067xx       00067x       02236x    JNV     Jump if No Overflow

0070xx       00070x       02242x    JV      Jump if Overflow

0072xx       00072x       02252x    JC      Jump if Carry
0073xx       00073x       02256x    JNC     Jump if No Carry

0077xx       00073x       02276x    JMP     Jump

016xxx       0016xx       026x2x    JSR     Jump to Subroutine

As well, there are related register-to-register instructions:

16-bit         Three-Address    Enlarged File
Register to    Register to      Register to
Register       Register         Register
------         -------------    -------------
140601                                              NOP       No Operation

1416xx         140000 016xxx    141666 0xxxxx       LBPC      Load Base with Program Counter

The Jump to Subroutine instruction uses the destination register to indicate which Short Base Register is used to store the return address; in the case of an Enlarged File register-to-register instruction, the Long Base Registers are also accessible through the use of the values from 8 to 15 in the destination register field.

The Load Base with Program Counter stores the return address in the same fashion as a Jump to Subroutine instruction, without performing a branch. This instruction can be used in the same fashion as the register-to-register form of the BAL (Branch and Link) instruction on the System/360 for initial setup of base register values in a program.


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