The formats of the instructions for this architecture are shown in the diagram below:
This diagram shows the instructions which occupy a full 32-bit instruction slot. The 16-bit instructions which the header format can call for in some instruction slots will be described on the next page.
In many cases, the instructions will be longer than 32 bits.
When an instruction contains a pSupp field, in Mode 2 and Mode 3 that field points to one of the sixteen extents of 16 bits into which the 256-bit instruction block may be divided. Such instructions cannot be used in Mode 0; in Mode 1, although that field may be present, the bits within it are not used, and so the field must contain all zeroes, as the instruction prefix indicates the length, and, if necessary, the position, of the additional portions of an instruction. In Mode 1+, in the additional instruction format made available in that mode, the field contains the length, in units of 16 bits, of the supplementary portion of the instruction.
In the case where an instruction has a pSupp field, following the illustration of the format of the 32-bit part of the instruction, after a gap, the format of the supplementary portion of that instruction is shown on the same line.
Note that, in several cases, including the format shown on the first line, the first two bits of an opcode field contain dotted boxes. This indicates that the format in question is distinguished from following ones by the fact that the first two bits of that opcode field may not both be ones.
When an instruction contains one or more pImm fields, in Mode 2 and Mode 3 each such field points to one of the thirty-two bytes composing a 256-bit instruction block. Such instructions cannot be used in Mode 0: in Mode 1, the values within these fields are not used, and the fields present must contain all zeroes; the required information to locate, and determine the length of, each immediate value used in the instruction is within the 16-bit instruction prefix. In Mode 1+, in the additional instruction format made available in that mode, each pImm field is a pointer to the last byte (the one with the least significant bits in it, the one located at the highest memory address) of the immediate value to which it refers, relative to the beginning of the instruction.
This additional portion of an instruction, the immediate value or values that may be associated with it, is not shown in the diagram; it consists of immediate data, and is thus in the big-endian version of the normal data format for the appropriate data type.
Note that the instructions in the diagram above are ordered.
000000 000000 to 163777 177777 Instructions without a C bit and without a pSupp field (Lines 1 through 8) 164000 ------ to 167777 ------ Prefixes 170000 000000 to 172777 177777 Instructions with a C bit and without a pSupp field (Lines 9 through 17) 174000 000000 to 174703 177777 Instructions with a C bit and with a pSupp field (Lines 18 through 31) 176000 000000 to 176777 177777 Instructions without a C bit and without a pSupp field (Lines 32 through 35) 177000 000000 to 177703 177777 Instructions without a C bit and with a pSupp field (Lines 36 through 46)
Ordering is numerical, except that the C bit and the pSupp field, if present, are skipped over for purposes of ordering.
Following the big-endian convention of numbering bits in a 32-bit word from bit 0 as the high-order most significant bit, and bit 31 as the low-order least significant bit, the C bit is bit 6, and the pSupp field occupies bits 10 to 13, of the main 32-bit word of the instruction.
Note that instructions without both the C bit and the pSupp field are split into two blocks within the opcode space.
Also, the area from 164000 to 1677777 is reserved for the 16-bit instruction prefixes used in Mode 1.
Instructions within each of the two blocks of instructions with a pSupp field are also further ordered by the length of the supplementary field, with length increasing as one proceeds ahead through the list.
Instructions within each of the two blocks of instructions with a C bit are additionally ordered in that the instructions with fields that may be switched between being register fields or pImm fields are placed at the beginning of those blocks, and the instruction format with two such fields is placed before that with only one such field.
As for how data values are stored:
Signed integer values are stored in binary two's complement format.
The standard types of floating-point numbers used by this architecture are shown below:
The 32-bit and 64-bit floating point formats correspond to that used in the IEEE 754 specification. A similar 48-bit floating-point format is added.
The 80-bit floating-point format, except for being stored in big-endian order, is that found on popular microcomputers, and the 128-bit format is the same format except for the significand being larger.
Note that the numbers for some of the instruction formats are circled.
These are the instruction formats that may appear in code which may be executed in Mode 0. (At one time, the term unblocked code was used for such code, but code for execution in Mode 1 or Mode 1+ is also not organized in instruction blocks.)
These instruction formats may not have either pSupp fields or pImm fields; however, instructions that may have pImm fields are allowed, but only when those fields are used as register fields instead.