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Memory-Reference Instructions

The instructions to be described on this page have the formats, taken from the main illustration of instruction formats on the first page of this section, shown in this diagram:

These are the five types of 32-bit memory-reference instructions.


The 32-bit form of basic load and store instructions is shown in lines 1 through 5.

For a memory-reference instruction, the five-bit destination register field specifies one of 32 registers, either the general-purpose registers for integer instructions, or the floating-point registers for floating-point instructions.

The index register field contains a number from 0 to 7, if it contains 0, the instruction is not indexed; if it contains any other value, that value indicates which general register is to be used as the index register for that instruction.

Lines 1 through five show the five possible formats for 32-bit memory-reference instructions.

In line 1, a field three bits in length indicates the base register. It may contain any value from 1 to 7, which indicates that a general register from 25 to 31 respectively is used as the base register.

Line 2 of the original diagram shows the second possibility: a 15-bit displacement is included in the instruction, and general register 16 contains the starting point of the 32,768-byte area of memory to which the values of this displacement may refer.

Line 5 of the original diagram shows the third possibility. Here, the displacement is 12 bits long, and there is a three-bit ssB field (short source base) adjacent to it.

If that field contains a number from 1 to 7, it indicates that a register from 17 to 23, respectively, is used as a base register, the contents of which point to a 4,096-byte area in memory.

If that field contains a 0, then one of the possibilities shown in lines 3 and 4 of the diagram apply.

Line 3 of the original diagram shows this possibility: if the ssB field, containing a 0, is followed by a 0, then program-relative addressing is indicated.

The instruction now contains an 11-bit displacement, which is in units of bytes, but now it is a signed two's complement value from -1,024 to 1,023, relative to the position immediately after the end of the instruction. One particularly important application of this addressing mode is at the beginning of a main program or a subroutine, where a Jump to Subroutine instruction having the following instruction as its destination can be used to initialize a base register by means of which adresses referring to the program code can be constructed.

Line 4 of the original diagram shows the format for two other addressing modes.

If the ssB field, containing a 0, is followed by 100, then it indicates Array Mode addressing.

Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit pointer to an array.

If indexing is present in the instruction, the contents of the selected register are added to that pointer in order to address an element of that array. Thus, Array Mode provides post-indexed indirect addressing in order to conveniently allow a program to refer to up to 512 arrays which are larger than 65,536 bytes in size without having to reload base registers in order to access them.

If the ssB field, containing a 0, is followed by 101, then Address Table addressing is indicated.

Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit constant containing the effective address of the instruction.

If indexing is present in the instruction, the contents of the selected register are added to the initial effective address formed by adding the contents of register 17 to the displacement, so as to change which 64-bit constant is taken as the effective address.

Thus, Array Mode addressing provides pre-indexed indirection, and Address Table addressing provides post-indexed indirection. Array Mode addressing is useful for accesing data in multiple large arrays without reloading base registers, and Address Table addressing is useful for such things as multi-way jump tables.

If the ssB field, containing a 0, is followed by 110, then Array Mode with Auto-Increment addressing is indicated. The displacement is in units of 64 bits, and the contents of base register 17 are added to the displacement after scaling to find the address to be used; this address may be indexed to form the effective address, and, in addition, after the memory location at the effective address so calculated is accessed, the index register is then incremented by the size of the operands of the instruction; incremented by one if the instruction acts on bytes, having eight added to it if the instruction acts on double-precision floating-point numbers, and so on. This includes adding six in the case of medium floating-point numbers.

If the ssB field, containing a 0, is followed by 111, then Array Mode with Flexible Auto-Increment addressing is indicated. Here, if the instruction is indexed, the index register must be one of registers 2, 4, or 6, and the amount by which it is incremented after memory access is found in the following register.


At this point, it may be noted that one programming technique that is not available in this Instruction Set Architecture (ISA) is to insert data in the locations immediately following a Jump to Subroutine instruction, so that the called routine can retrieve parameters in that data, and then increment the return pointer before using it to return so that the data is skipped over.

This also means that one cannot embed a routine name immediately following the initial Jump to Subroutine instruction used for initializing the first base register as a way to facilitate documentation of errors.

That is because of how instructions are organized: in 256-bit blocks which consist of 32 or 64 bits of header information, followed by 32 to 224 bits of pure 32-bit instructions, with immediate values and other additional portions of those instructions placed after the instructions.

It is intended that compilers and assemblers will treat the supplementary portions of instructions as aligned on 16-bit boundaries, and will order immediate data by placing the items with the largest alignment width at the end of the block, and then the items with the next-largest alignment width in front of them, and so on. This way, all the immediate data will be correctly aligned, so as to be consistent with the maximum speed of operation. In most cases, this means the widest items are placed at the end, but 48-bit Medium floating-point numbers, this length being only a multiple of 16 bits, have an alignment width of 16 bits and so are treated as "shorter" than 32-bit items in this sense.

The opcodes of the basic memory-reference instructions are:

000xxx xxxxxx LB       Load Byte
004xxx xxxxxx STB      Store Byte
010xxx xxxxxx ULB      Unsigned Load Byte
014xxx xxxxxx IB       Insert Byte
020xxx xxxxxx LH       Load Halfword
024xxx xxxxxx STH      Store Halfword
030xxx xxxxxx ULH      Unsigned Load Halfword
034xxx xxxxxx IH       Insert Halfword
040xxx xxxxxx L        Load
044xxx xxxxxx ST       Store
050xxx xxxxxx UL       Unsigned Load
054xxx xxxxxx I        Insert
060xxx xxxxxx LL       Load Long
064xxx xxxxxx STL      Store Long
070xxx xxxxxx LA       Load Address

100xxx xxxxxx LM       Load Medium
104xxx xxxxxx STM      Store Medium
110xxx xxxxxx LF       Load Floating
114xxx xxxxxx STF      Store Floating
120xxx xxxxxx LD       Load Double
124xxx xxxxxx STD      Store Double
130xxx xxxxxx LQ       Load Quad
134xxx xxxxxx STQ      Store Quad

The Load Address instruction places the effective address of the instruction in the destination general register, instead of loading a value at the effective address from memory.


The conditional jump instructions, shown on line 6, have the opcodes:

0741xx xxxxxx JL       Jump if Low
0742xx xxxxxx JE       Jump if Equal
0743xx xxxxxx JLE      Jump if Low or Equal
0744xx xxxxxx JH       Jump if High
0745xx xxxxxx JNE      Jump if Not Equal
0746xx xxxxxx JHE      Jump if High or Equal
0747xx xxxxxx JNV      Jump if No Overflow
0750xx xxxxxx JV       Jump if Overflow

0752xx xxxxxx JC       Jump if Carry
0753xx xxxxxx JNC      Jump if No Carry

0756xx xxxxxx DXJUZ    Decrement index and Jump Unless Zero
0757xx xxxxxx J        Jump

These instructions cause a transfer of control to the instruction located at the effective address of this instruction. As the displacement is a byte value, transfer of control to the second of two 16-bit instructions is possible.

In these instructions, the base register field is its normal three bits in length, with the values 1 through 7 in this field indicating the use of the general registers 25 through 31 respectively as the base register. A value of zero functions in the same way as it does in the case of a two-bit field.

The available addressing modes for these instructions are the same as those for the memory-reference instructions as shown in lines 1 through 4, but they are not repeated in the illustration.

The Decrement index and Jump Unless Zero instruction cannot be indexed; instead, it decrements the contents of the register indicated in the index register field; if the result is zero, it falls through to the next instruction; otherwise it branches to the effective address. This instruction is used to make it simpler to write some simple loops.


The subroutine jump instruction, shown on line 7, has the opcode:

076x0x xxxxxx JSR      Jump to Subroutine

In addition to branching to the effective address of the instruction, it stores a return address in the register indicated by the return register field. The return register field is four bits long, and numbers from 0 to 15 in that field indicate general registers 16 through 31 respectively.

The return address may be stored in one of registers 25 through 31, in register 16, or in one of registers 17 through 23, so that an unconditional jump with no indexing and a zero displacemnt may return from the subroutine. Normally, a register in the range from 17 through 23 is perhaps the most likely to be used, as those are the registers associated with 12-bit displacements.

The value of the return address is the address of the next 32-bit instruction slot following the instruction.

In the case where a Jump to Subroutine instruction is in the last 32-bit instruction slot used for instructions in a given block, the return address is the beginning of the following instruction block; no attempt is made to parse the following instruction block to determine if its header is 32 bits, 64 bits, or (in Mode 4 or 5) 16 bits in length. In general, in addition to branching to a 32-bit instruction slot which contains an instruction, and branching to the second 16-bit instruction in a 32-bit instruction slot if it contains two 16-bit instructions, it is also possible to branch to an instruction block as a whole by branching to the address of the beginning of the block.

Note that the 32-bit subroutine jump may not be indexed.

Branching to the second 32-bit instruction slot in an instruction block, where that slot contains the second half of the header rather than an instruction, does not need to be supported by a conformant implementation of this architecture.


When control flow guidance is enabled, a random number generated by the processor on power up is used in combination with the return address in a jump to subroutine instruction to produce a hash which is then condensed to 12 bits. Instead of saving only the return address, the 64-bit return address now consists of the 12-bit hash digest, followed by a 52-bit return address. Thus, when control flow guidance is enabled, the total virtual address space of the machine is limited to 52 bits. (Incidentally, this means that it is not necessary to mask out the hash to use a return value to initialize a base register.)

Also, when control flow guidance is enabled, the return address is also placed on a hidden stack which is used to confirm the correctness of addresses used when returning from subroutines. This is avoided when the target of a subroutine call instruction indicates itself as the target of a non-advancing jump to subroutine instruction, intended only to do something such as initializing a base register. Also, since the return from a jump to subroutine instruction is simply an ordinary jump instruction, with the return address placed in the base register that it uses, the distinction between an ordinary jump instruction, which does not pop a return address from the hidden stack, and a return from subroutine instruction, which does, is made in the prefix at the jump target which indicates that the target location is a legitimate jump target.


Lines 8 and 9 illustrate the format of the 32-bit version of the multiple register memory reference instructions.

Due to the limited available space in a 32-bit instruction, only two of the three formats for indicating a memory address are used:

in line 6, the same one as shown in line 2, and in line 7, the same one as shown in line 3.

Also, indexing is not available with the 32-bit form of these instructions.

The available instructions in this format are:

140xxx LML   Load Multiple Long
142xxx STML  Store Multiple Long
144xxx LMQ   Load Multiple Quad
146xxx STMQ  Store Multiple Quad
150xxx LMSV  Load Multiple Short Vector
152xxx STMSV Store Multiple Short Vector
154xxx LMXR  Load Multiple Extended Raw
156xxx STMXR Store Multiple Extended Raw

The load and store multiple long instructions load and store the 64-bit contents of the specified integer registers, in successive locations at the destination address.

The load and store multiple quad instructions load and store the 128-bit contents of the specified floating-point registers.

The load and store short vector registers load and store the 256-bit contents of the specified short vector registers. Although the dRl and dRh fields of the instruction are five bits long, as there are only sixteen short vector registers, the first bit of each field is to always be zero.

The load and store extended raw instructions load and store the 160-bit contents of the specified pairs of floating-point and type extension registers, with the contents of the floating-point register being placed first, in the locations with the lower addresses forming the high-order bits of the combined 160-bit field.


Line 10 illustrates another form of subroutine jump instruction that can serve a special purpose.

It can only have a short format address, and it cannot be indexed.

This makes room for a four-bit region in the instruction containing a 4-bit source mode field.

The purpose of these fields is to label code with its type at subroutine entry points, making it possible, when using a special subroutine call instruction, to call a subroutine knowing the address of its entry point, but not the mode in which the code is written.

This instruction has the opcode:

160x0x xxxxxx  SSJ Short Subroutine Jump

It occurs at the beginning of a subroutine, its usual purpose being not to call another subroutine, but to load the register specified as its return register with the location of the address that follows it in order to initialize a base register for that subroutine.

The diagram above illustrates the format of instructions used to switch, in user mode, between the available methods of representing or organizing program code.

In a cross-mode subroutine jump instruction:

The dM field specifies the destination mode: the mode of the subroutine to which a transfer of control is taking place.

The sM field is set to reflect the mode currently in effect for the code in which the instruction is located. If it is not set correctly, return from the subroutine will not take place properly.

The action of this instruction is:

The address of the cross-mode subroutine jump instruction itself, plus one, is placed in the integer register indicated in the dR field.

Control is transferred to the address indicated by the contents of the pointer register (pR) field, so normally the pR field will be loaded by a preceding Load Address instruction. This limitation of the instruction was necessary to allow room for the sM, and dM fields in the instruction as well as a return register.

The instructions with this format are:

167600 00xxxx JSRXM    Jump to Subroutine cross-mode
167600 04xxxx JSRXMU   Jump to Subroutine cross-mode Unknown

The foregoing text described the JSRXM instruction.

The JSRXMU instruction is similar, except that the dM field is not used, and must contain zeroes. The sM field is used in this instruction, and must be set correctly.

At the destination address of the JSRXMU instruction, a 32-bit Short Subroutine Jump instruction must be present, as it is this form of the subroutine jump that also contains an sM field.


This might seem like an unusual requirement. Why should the first thing that a subroutine would do be to call another subroutine? Wouldn't that result in an infinite level of nesting? (Well, not really, since what must be present at the effective address of the JSRXMU instruction is an SSJ instruction, not another JSRXMU instruction, and the SSJ instruction has no such requirement.)

However, neither a Jump to Subroutine nor a Short Subroutine Jump instruction need necessarily be used to call a subroutine. Instead, the fact that it provides a return address in a specified register may be useful in initializing the first base register used by a program. Thus, it is expected that independently-compiled subroutines, which can't use base registers shared with the calling program, will start with some form of Jump to Subroutine instruction that uses program-relative addressing so that instead of calling a distant subroutine, it will simply branch to where it needs to continue on.

This is comparable to the use of the BALR (Branch and Link Register) instruction on the IBM System/360 computer at the beginning of subroutines.

To allow a routine to be called using a JSRXMU instruction, the SSJ instruction specifically must be used, so that the mode in which the code being called is running can be determined from its sM and sIM fields.

The sM field in that instruction is read to set the instruction mode to use in processing the program code at the destination address. The return address provided by the JSRXMU instruction also points to the second byte of the JSRXMU instruction, exactly as with the JSRXM instruction.

The other instructions are simply branch instructions, which do not leave a return address. Instead, the last four bits of the rR field contain the branch condition, and the first bit of that field is a zero.

The dM field is used as in the JSRXM instruction. The sM field is not used in these instructions, as they are jump instructions and not subroutine jump instructions with a return address, and must contain zero.

Return from a Jump to Subroutine cross-mode instruction is handled as follows:

The subroutine will be an ordinary subroutine that is designed to be called with normal Jump to Subroutine instructions. Therefore, it will perform return to the caller by means of an ordinary jump instruction, set up to use the return address without a displacement, normally by specifying the return address register as the base register with an address value of zero.

Because cross-mode jump instructions specify the mode of their target, they may not be used to return from a subroutine if that subroutine is to work properly when called by a Jump to Subroutine cross-mode instruction.

Instructions are, in all the available instruction modes, aligned on 16-bit boundaries. Therefore, jump instructions function normally when their effective address is an even number.

When the effective address of any jump instruction is an odd number, it will be assumed that return from a subroutine called with a Jump to Subroutine cross-mode instruction is taking place, and therefore the following operations will be performed:

The byte at the effective address will be fetched. This byte will be assumed to be the second byte of a JSRXM or JSRXMU instruction. (At some point, a check will be made to determine if the other bits of the 32-bit word in which that byte is contained are consistent with that. If not, the program will trap with an exception.) The sM field therein will be read, and the instruction mode of the computer (or, more accurately, the current thread) will be set to the value it indicates.

Transfer of control will take place to the instruction following the JSRXM or JSRXMU instruction. This may be done directly; in the case of mode 0 and mode 1, by a jump to the effective address of the branch instruction plus three, and in the case of modes 2 and 3, by reading the entire block in which the JSRXM or JSRXMU instruction is contained, and carrying out appropriate processing, or it may be done indirectly, by transferring control to the JSRXM or JSRXMU instruction itself with the machine state set so that it is treated as if it was predicated out. The latter case does not, of course, remove the need in modes 2 and 3 to read the whole block containing the JSRXM instruction, it may just avoid the need to duplicate some circuitry at the cost of additional cycles.

Also, note that 32-bit instructions may only begin on 32-bit boundaries in Mode 0 and Mode 12 through Mode 15. However, they may begin on any 16-bit boundary in Mode 2 through Mode 7.

Therefore, in the case where a program in one of the former group of modes executes a JSRXM or JSRXMU instruction, the return address will always be an odd number of the form 4n+1 for integer n. But when code in Mode 2 through Mode 7 excecutes a JSRXM or JSRXMU instruction the return address may be a general odd number, only of the form 2n+1 for integer n.

As the 32-bit forms of the conditional jump instructions and the jump to subroutine instruction impose some limitations on addressing modes, there are also longer full versions of those instructions, with the formats shown below:

These instructions have the opcodes:

176x60 1001xx TL       Transfer if Low
176x60 1002xx TE       Transfer if Equal
176x60 1003xx TLE      Transfer if Low or Equal
176x60 1004xx TH       Transfer if High
176x60 1005xx TNE      Transfer if Not Equal
176x60 1006xx THE      Transfer if High or Equal
176x60 1007xx TNV      Transfer if No Overflow
176x60 1010xx TV       Transfer if Overflow

176x60 1012xx TC       Transfer if Carry
176x60 1013xx TNC      Transfer if No Carry

176x60 1017xx T        Transfer

176x60 104xxx TSR      Transfer to Subroutine

176x60 110xxx TXM      Transfer cross-mode

and, in the case of the equivalent of the Jump to Subroutine instruction, as well as the case of the cross-mode jump, indexing is now available.

As well, it was possible, by dint of careful structuring of how instructions are distributed in opcode space, to provide a version of the cross-mode subroutine call instruction with a supplementary field:

The instructions in this form have the opcodes:

172x4x 0xxxxx TSRXM   Transfer to Subroutine cross-mode
172x4x 100xxx TSRXMU  Transfer to Subroutine cross-mode Unknown

The sM field is required in both instructions so that return from a cross-mode subroutine is possible. Note that in modes 2 through 7, it will be necessary for the return from the subroutine to properly evaluate the length of the instruction to continue with the following instruction. For the TSRXMU instruction, the dM field is not used, and must contain zero.


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