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Instruction Format

The formats of the instructions for this architecture are shown in the four diagrams below.

First, the instructions that are 32 bits in length which can never affect the condition code bits, as they perform functions such as load and store, or jump are as follows in normal format I program code:

In some block formats, the format of the memory-reference instructions is changed, so that they can fit into a reduced amount of available opcode space, that available to format II instructions, where the instructions that are 32 bits or longer must begin witn a 1:

In other block formats, the format of the memory-reference instructions is changed to reduce the amount of opcode space they consume further; here, not only do all 32-bit instructions begin with 1, but some additional initial combinations of bits are left unused; these are the format III instructions:

The amount of opcode space is reduced by restricting the basic memory-reference instructions to aligned operands.

Finally, there are the format IV instructions, where the memory-reference instructions take up the same amount of opcode space as in format I; these instructions allow 32-bit memory reference instructions other than load and store instructions, this possibly saving an instruction on occasion, at the cost of only working with registers 0 through 7 of both the integer and floating-point register banks, instead of all the registers from 0 to 31:

Only these instructions differ between the four instruction formats, although depending on the specific block format used, some or all instructions longer than 32 bits may not be available, or the contents of the pSupp field may be affected.

Format I provides the most complete instruction set, all the forms of the basic memory-reference instructions are available. A 32-bit instruction may begin with any combination of four bits except 1100.

Format II imposes the restriction that the basic memory-reference instructions can only refer to aligned operands. This also eliminates some of the advanced addressing modes from those instructions, and leads to the Load Address instruction not being available among the basic memory-reference instructions. In this format, a 32-bit instruction may not start with a zero, but may begin with any combination of four bits that starts with a one.

Format III instead limits the addressing modes available; if a basic-memory instruction uses indexing, it may not use 16-bit displacements. This is a more severe limitation on basic memory-reference instructions; in this format, a 32-bit instruction may not begin with a zero, and it also may not begin with either of the two four-bit combinations 1011 and 1100.

Also, in any of these formats, 32-bit instruction may not have 1111111 as their first seven bits.

Format IV uses the same opcode space as Format I, but is modified to permit memory-reference instructions to perform arithmetic operations, at the cost of only working with registers 0 through 7.


Second, the instructions that are 32 bits long which perform arithmetic operations, and so have a C bit which will be set to 1 if the instruction is to affect the condition code bits:

Note that some of these instructions may have immediate values, or, more properly pseudo-immediate values, as shown in lines 2, 4 and 7 of the diagram, as opposed to a true immediate value as shown in line 5; in that case, they will take up more than 32 bits of space, but the immediate value is, for purposes of this classification, not considered part of the instruction itself.

Third, the instructions that are longer than 32 bits, and so have a pSupp field to point to the extra portion of the instruction, and have a C bit because they perform a calculation:

And finally, fourth are the instructions that are longer than 32 bits but do not have a C bit:

These diagrams show the instructions which occupy a full 32-bit instruction slot. The 16-bit instructions which the header format can call for in some instruction slots will be described on the next page.

In many cases, the instructions will be longer than 32 bits.


When an instruction contains a pSupp field, in Mode 2 and Mode 3 that field points to one of the sixteen extents of 16 bits into which the 256-bit instruction block may be divided.

In the second header format, instructions containing that field may be present, the bits within it are not used, and so the field must contain all zeroes, as the supplementary bits of the instruction are in successive 18-bit instruction slots that begin with 11. In the fourth and fifth header formats, the pSupp field may be used normally, or the bits within it can be zero so that the supplementary bits are placed in the normal fashion as is the only option with the remaining header types.

In the case where an instruction has a pSupp field, following the illustration of the format of the 32-bit part of the instruction, after a gap, the format of the supplementary portion of that instruction is shown on the same line.

Note that, in several cases, including the format shown on the first line, the first two bits of an opcode field contain dotted boxes. This indicates that the format in question is distinguished from following ones by the fact that the first two bits of that opcode field may not both be ones.

When an instruction contains one or more pImm fields, in Mode 2 and Mode 3 each such field points to one of the thirty-two bytes composing a 256-bit instruction block. Such instructions cannot be used in blocks having the first type of header, since no decode field is present in that header format to indicate space for pseudo-immediate values; unlike the supplementary portion of an instruction, pseudo-immediates may not be cut up and placed within 18-bit instruction slots beginning with 11.

This additional portion of an instruction, the immediate value or values that may be associated with it, is not shown in the diagram; it consists of immediate data, and is thus in the big-endian version of the normal data format for the appropriate data type.


Note that the instructions in the diagrams above are ordered.

000000 000000 to 167377 177777  Instructions without a C bit and without a pSupp field
170000 000000 to 173777 177777  Instructions with a C bit and without a pSupp field
174000 000000 to 175777 177777  Instructions with a C bit and with a pSupp field
176000 000000 to 176777 177777  Instructions without a C bit and with a pSupp field

Instructions are not, however, in strict numerical order. The C bit and the pSupp field are ignored in ordering instructions, and, thus, since bits past those bits are used where a C bit is present, in the instructions without a C bit that come afterwards, the bit in that position is treated as less significant than bits 5 and 10 that come after it.

Instructions within each of the two blocks of instructions with a pSupp field are also further ordered by the length of the supplementary field, with length increasing as one proceeds ahead through the list.

In several block formats, instructions with a pImm field are not available.

In the eighteenth and nineteenth block formats, while instructions with a pImm field are not available, the instructions longer than 64 bits with a pSupp field are available; in ese formats, the pSupp field no longer functions as a pointer, but instead indicates the length of the instruction, as follows:

0000    48 bits
0001    64 bits
0010    80 bits
0011    96 bits

In the diagrams of instruction formats above, the instructions within each of the two blocks of instructions with a C bit are additionally ordered in that the instructions with fields that may be switched between being register fields or pImm fields are placed at the beginning of those blocks, and the instruction format with two such fields is placed before that with only one such field.


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