The formats of the basic instructions for this architecture are shown in the two diagrams below.
The formats of the 16-bit instructions, along with the 32-bit instructions
0 as their first bit are shown here:
The 32-bit instructions shown here are primarily the register-to-register operate instructions, but the load and store multiple memory-reference instructions are also included.
The instructions shown in lines 2, 3, and 5 of the third and fourth sections of the diagram (a section of the diagram is indicated by the numbering sequence of the lines starting over) are only available in those block formats which specify that some instruction slots are not to be decoded.
In addition to the normal banks of 32 integer and 32 floating-point registers, to facilitate high speed operation in the VLIW block formats, there are extended banks of 128 integer and 128 floating-point registers. The instructions the formats of which are shown in lines 9, 10, and 11 of the fourth and final section of the diagram are the ones which access these registers.
In line 9, the instruction format includes four page bits, to be prefixed to the contents of the three-bit fields specifying the destination, operand, and source registers, so for these instructions, the 128 registers are divided into sixteen groups of eight.
In line 10, the instruction format includes two page bits, to be prefixed to the contents of the five-bit fields specifying the destination and source registers, so for these instructions, the 128 registers are divided into four groups of thirty-two.
In line 11, instructions are provided where the destination register belongs to one of the regular banks of 32 registers, and the source register belongs to the corresponding bank (integer or floating-point) of the extended banks of 128 registers.
The instruction format shown in line 12 of the fourth and final section of the diagram may only be present in the first instruction slot of a block; as well as being an instruction with an immediate operand, it also serves as the header for the block, including the decode field to specify that some instructions are not to be decoded and therefore to make itself, and other instructions with immediate operands, permissible in that block.
The second section of the diagram shows the load and store multiple instructions; these instructions are put in this portion of the opcode space due to insufficient opcode space being available elsewhere.
An integer multiple-register instruction has a source address that is aligned
on 64-bit boundaries; only a single bit is always zero at the end of the address
area because this portion of the instruction is shifted over two places, thus
making room for the first bit of the second half of the instruction always being
1 to distinguish 32-bit instructions, usually register-to-register
operate instructions, in this section from pairs of 16-bit instructions.
Similarly, the floating multiple-register instructions have source addresses
aligned on 128-bit boundaries, the width of an extended-precision floating-point
number, and thus there is room to put the bits
01 at the end of
each address to indicate the type on which the instruction operates. This method
of reducing the opcode space required for instructions that operate only on aligned
data was previously used in the SEL32 microcomputer.
Note that specific ranges of opcode space have not been shown in lines six, seven, and eight of the fourth and final section of the diagram to distinguish between the general single operand instructions, the shift instructions, and the plain immediate instructions with 8-bit immediates.
This area of the opcode space will also be used for other specialized instructions, such as the Supervisor Call instruction.
The formats of the 32-bit instructions
1 as their first bit are shown here:
These instructions are the memory-reference instructions.
The instructions in lines 16 through 19 also have available the same addressing modes as shown in lines 13 through 15 for the medium precision floating-point instructions, and above for the various integer floating-point instructions, these modes are simply not repeated in the diagram for brevity.
There are five possible formats for 32-bit memory-reference instructions. In Extended Mode, there are instructions with all five modes; here, all five modes are used as well, but they are available to different instructions.
In lines 1, 4, 7, 10, and 13, we see the mode where a field three bits in length indicates the base register. It may contain any value from 1 to 7, which indicates that a general register from 25 to 31 respectively is used as the base register.
Lines 2, 5, 8, 11, and 14 of the diagram above, as well as line 27, show the second possibility: a 15-bit displacement is included in the instruction, and general register 16 contains the starting point of the 32,768-byte area of memory to which the values of this displacement may refer.
Line 3, 6, 9, 12, and 15, along with line 28, of the diagram above show the third possibility. Here, the displacement is 12 bits long, and there is a three-bit ssB field (short source base) adjacent to it.
If that field contains a number from 1 to 7, it indicates that a register from 17 to 23, respectively, is used as a base register, the contents of which point to a 4,096-byte area in memory.
If that field contains a 0, then one of the possibilities shown in lines 4 and 5 of the diagram apply.
Line 29 of the diagram above shows this possibility: if the ssB field, containing a 0, is followed by a 0, then program-relative addressing is indicated.
The instruction now contains an 11-bit displacement, which is in units of bytes, but now it is a signed two's complement value from -1,024 to 1,023, relative to the position immediately after the end of the instruction. One particularly important application of this addressing mode is at the beginning of a main program or a subroutine, where a Jump to Subroutine instruction having the following instruction as its destination can be used to initialize a base register by means of which adresses referring to the program code can be constructed.
Line 30 of the diagram above shows the format for two other addressing modes.
If the ssB field,
containing a 0, is followed by
100, then it indicates Array Mode addressing.
Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit pointer to an array.
If indexing is present in the instruction, the contents of the selected register are added to that pointer in order to address an element of that array. Thus, Array Mode provides post-indexed indirect addressing in order to conveniently allow a program to refer to up to 512 arrays which are larger than 65,536 bytes in size without having to reload base registers in order to access them.
If the ssB field,
containing a 0, is followed by
101, then Address Table addressing is indicated.
Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit constant containing the effective address of the instruction.
If indexing is present in the instruction, the contents of the selected register are added to the initial effective address formed by adding the contents of register 17 to the displacement, so as to change which 64-bit constant is taken as the effective address.
Thus, Array Mode addressing provides pre-indexed indirection, and Address Table addressing provides post-indexed indirection. Array Mode addressing is useful for accesing data in multiple large arrays without reloading base registers, and Address Table addressing is useful for such things as multi-way jump tables.
If the ssB field, containing a 0, is followed by
110, then Array Mode with Auto-Increment addressing
is indicated. The displacement is in units of 64 bits, and the contents of base register 17 are added
to the displacement after scaling to find the address to be used; this address may be indexed to form
the effective address, and, in addition, after the memory location at the effective address so calculated
is accessed, the index register is then incremented by the size of the operands of the instruction;
incremented by one if the instruction acts on bytes, having eight added to it if the instruction acts
on double-precision floating-point numbers, and so on. This includes adding six in the case of medium
If the ssB field, containing a 0, is followed by
111, then Array Mode with Flexible Auto-Increment
addressing is indicated. Here, if the instruction is indexed, the index register must be one of
registers 2, 4, or 6, and the amount by which it is incremented after memory access is found in the
The Jump on Flag instructions shown in line 23 may require some explanation. While having a C bit to enable setting the condition codes in operate instructions will usually address issues resulting from the delay, in a pipelined architecture, for the result of an instruction to become available, occasionally a compiler, for reasons of optimization, may extensively re-order operations in a program.
The flag bit mechanism already exists as the most convenient way to handle predicated instructions. Having a Jump on Flag instruction allows issues from the re-ordering of instructions to be conveniently dealt with, without the burden on opcode space imposed by the solution used in the PowerPC of having multiple sets of condition codes.
The alternate load/store instructions in lines 24 and 25 may not be indexed; they provide the ability to load and store data in less common formats such as decimal floating-point and compatible floating-point.
Lines 26 to 29 show the unaligned load/store instructions. As these instructions may be indexed, they are limited to four possible destination registers, to conserve opcode space. The destination register field is to be interpreted as follows:
Field Register 00 0 01 8 10 16 11 24
In this way, unaligned data can be brought to, and sent from, any of the four groups of eight registers.
The Execute instructions, as shown in line 30, have the following values for the opcode field:
Opcode Instruction 0 XFC Execute from Code 1 XFD Execute from Data
In an Execute instruction, the operand and
destination register fields both indicate an integer register from 16
through 23. The operand register contains a bit mask; the bits in the
instruction at the source address which correspond to bits in the least
significant 32 bits of the operand register that are
replaced by the corresponding bits in the destination register.
The resulting instruction, as modified, is then performed.
It may not be another Execute instruction, nor may a pair of 16-bit instructions be executed.
In the case of the Execute from Code instruction:
The block in which the instruction is contained is analyzed to check for the possibility that it may contain instructions in the Extended format instead prior to executing the instruction.
In that case, it is the first 32 bits of the instruction, exclusive of prefix bits, that are modified. The instruction may be a single 16-bit instruction; in that case, the least significant 16 bits of the operand and source registers are ignored, and only bits 32 through 47 of those registers are involved in modifying the instruction.
If the instruction is a subroutine jump instruction, the return address is based on the source memory operand, not the Execute instruction; if the instruction is a relative branch instruction, the branch is relative to the source memory operand.
In the case of the Execute from Data instruction:
The block in which the instruction is contained is not analyzed to check for the possibility that it may contain instructions in the Extended format instead prior to executing the instruction, as the instruction being executed is considered to be stored as a 32-bit data item and not embedded within existing program code.
If the instruction is a subroutine jump instruction, the return address is based on the Execute instruction, not the source memory operand; if the instruction is a relative branch instruction, the branch is relative to the Execute instruction.
For both Execute instructions:
At the time of the return from the subroutine, or the relative branch, the block containing that destination will be fully analyzed, so that subsequent execution will be based on decoding of instructions with the appropriate format.