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16-bit Instructions

The instructions to be described on this page have the formats shown in this diagram:

The 16-bit instructions do not include memory-reference instructions, or the subroutine jump instruction. However, while the set of 16-bit instructions is therefore not complete in itself, it is sufficient that a large proportion of the instructions in a program could be 16-bit instructions.

These instructions contain a two bit page field, followed by a three-bit destination register field, and a three bit source register field. The five-bit value from 0 to 31 which indicates the destination register is formed by concatenating the page field and the destination register field, and that which indicates the source register field is similarly formed by concatenating the page field and the source register field.

In this way, even when 16-bit instructions are used, four threads of calculation, each using a different group of eight registers, can be interleaved in a sequence of code, allowing more instructions to execute either simultaneously or in rapid succession before a dependency is encountered.

Line 1 gives the format of the operate instructions. Integer instructions reference the integer registers, and floating-point instructions reference the floating-point registers, as might be expected.

There are 96 possible opcodes, as the first two bits of an opcode may not be both 1, as these combinations are reserved for other 16-bit instructions.

The opcodes (with the first four bits appearing along the top of the chart, and the last three bits appearing on the right) are:

0000   0001   0010   0011   0100   0101   0110   0111   1000   1001   1010   1011
SWB    IB     SWH    IH     SW     I      SWL           SWM    SWF    SWD    SWQ    000
CB            CH            C             CL            CM     CF     CD     CQ    001
LB     ULB    LH     ULH    L      UL     LL            LM     LF     LD     LQ     010
STB    XB     STH    XH     ST     X      STL    XL     STM    STF    STD    STQ    011
AB     NB     AH     NH     A      N      AL     NL     AM     AF     AD     AQ     100
SB     OB     SH     OH     S      O      SL     OL     SM     SF     SD     SQ     101
              MH     MEH    M      ME     ML     MEL    MM     MF     MD     MQ     110
              DH     DEH    D      DE     DL     DEL    DM     DF     DD     DQ     111

The different instructions are:

For integer types:

SW    SWAP                Exchange the contents of the source and destination locations

C     COMPARE             Subtract the contents of the source location from the contents of
                          the destination location, but with the operation modified so that
                          overflow cannot possibly result, and set the condition codes appropriately
                          without modifying the destination location 

L     LOAD                Place the contents of the source operand in the destination register;
                          if the type involved is smaller than the register, perform sign extension

ST    STORE               Fill the destination location from the least significant part of the
                          source location

A     ADD                 Add the contents of the source and destination locations, placing the
                          result in the destination location

S     SUBTRACT            Subtract the contents of the source location from those of the destination
                          location, placing the result in the source location

M     MULTIPLY            Multiply the contents of the source and destination locations, placing the
                          least significant part of the result of the same length as the two input
                          operands in the destination location, with sign extension if that is shorter
                          than the length of the destination register

D     DIVIDE              Divide the contents of the source location by the contents of the destination
                          location, placing the quotient in the destination location

I     INSERT              Fill the least significant bits of the destination register with
                          the contents of the source location, leaving the rest of the destination
                          register unaffected

UL    UNSIGNED LOAD       Fill the least significant bits of the destination register with
                          the contents of the source location, and clear the remaining more
                          significant bits of the destination register

X     EXCLUSIVE OR        Perform a bitwise Exclusive OR operation between the contents of the source
                          and destination locations, placing the result in the desination location

N     AND                 Perform a bitwise Logical AND operation between the contents of the source
                          and destination locations, placing the result in the desination location

O     OR                  Perform a bitwise Logical OR operation between the contents of the source
                          and destination locations, placing the result in the desination location

ME    MULTIPLY EXTENSIBLY Multiply the contents of the source and destination locations. Take the
                          full product, as an integer having twice the size as that of the source
                          and the destination, and:
 - in the case of the halfword and integer versions of the instruction, place it in the destination
   register, with sign extension in the halfword version;
 - in the case of the long version of the instruction, place the most significannt half of the result
   in the destination register, which must be an even-numbered register, and place the least significant
   half of the result in the register following

DE    DIVIDE EXTENSIBLY   Divide a destination operand of twice the length of that indicated by the
                          instruction type (and located as the result of the MULTIPLY EXTENSIBLY
                          instruction) by the source operand; store the double length quotient
                          in the destination location (again following the MULTIPLY EXTENSIBLY
                          result placement) and the single length remainder in the next register
                          following those that are used.
                             Whenever a result is not wide enough to fill a register, sign extension
                          is performed.
                             Division is performed giving a result as if both operands were converted
                          to positive numbers before starting, with the signs then set afterwards
                          to give a correct result based on the actual signs of the operands. Thus
                          both the quotient and the remainder will be positive or zero if the dividend
                          and divisor have the same sign, and both will be negative or zero if they
                          are of opposite signs.

The possible integer types, and the suffixes that indicate them, are:

B     BYTE      An 8-bit two's complement integer
H     HALFWORD  A 16-bit two's complement integer
      INTEGER   A 32-bit two's complement integer
L     LONG      A 64-bit two's complement integer

The integer registers are 64 bits long, to contain the longest of these types.

The available floating-point operations are SWAP, LOAD, STORE, ADD, SUBTRACT, MULTIPLY, and DIVIDE. Their functions are basically the same as those of the corresponding integer operations, except that floating-point arithmetic is performed.

The possible floating-point types for 16-bit instructions, and the suffixes that indicate them, are:

M     MEDIUM    A 48-bit floating-point number (preferably aligned on 16-bit boundaries)
F     FLOATING  A 32-bit floating-point number
D     DOUBLE    A 64-bit floating-point number
Q     QUAD      A 128-bit floating-point number

with their formats as indicated within this diagram:

These instructions are then also suffixed RC for Register Compact to indicate the addressing mode.


Lines 2 through 5 of the diagram illustrate the shift and rotate short instructions. These are:

060xxx LSLLC   Logical Shift Left Long Compact
061xxx LSRLC   Logical Shift Right Long Compact
062xxx RLLC    Rotate Left Long Compact
063xxx ASRLC   Arithmetic Shift Right Long Compact

0640xx LSLC    Logical Shift Left Compact
0650xx LSRC    Logical Shift Right Compact
0660xx RLC     Rotate Left Compact
0670xx ASRC    Arithmetic Shift Right Compact

0644xx LSLHC   Logical Shift Left Halfword Compact
0654xx LSRHC   Logical Shift Right Halfword Compact
0664xx RLHC    Rotate Left Halfword Compact
0674xx ASRHC   Arithmetic Shift Right Halfword Compact

0646xx LSLBC   Logical Shift Left Byte Compact
0656xx LSRBC   Logical Shift Right Byte Compact
0666xx RLBC    Rotate Left Byte Compact
0676xx ASRBC   Arithmetic Shift Right Byte Compact

Logical right and left shifts insert zeroes; the arithmetic right shift inserts a copy of the existing value of the most significant bit into the leftmost position of the word so as to maintain the sign as either negative or non-negative.

An arithmetic left shift inserts zeroes into the leftmost end of a number regardless of its sign, just like a logical left shift, but it differs in that the overflow bit is set if a left shift results in a change of the sign of the value being shifted, instead of merely a carry out of that value; this difference is, however, not applicable to short instructions, as they may not alter the condition codes, not having space for a C bit.

In the 16-bit short instructions, there is no available separate region of opcode space for the rotate instructions, and so instead the arithmetic left shift is replaced by rotate left.


Line 6 of the diagram shows the branch instructions.

The displacement is an 8-bit signed value, in two's complement form, which may vary from -128 to +127. The displacement is in units of 32 bits. No attempt is made to skip over values corresponding to the 32-bit instruction slots containing header information. A displacement of zero refers to the instruction slot following that in which the instruction is located, whether the instruction is found in the first or second half of the instruction slot in which it is located, therefore a branch with a displacement of zero is only equivalent to a no-operation if it occurs in the second half of an instruction slot.

The available branch instructions are:

16 bit

0704xx BL    Branch if Low
0710xx BE    Branch if Equal
0714xx BLE   Branch if Low or Equal
0720xx BH    Branch if High
0724xx BNE   Branch if Not Equal
0730xx BHE   Branch if High or Equal
0734xx BNV   Branch if No Overflow
0740xx BV    Branch if Overflow

0750xx BC    Branch if Carry
0754xx BNC   Branch if No Carry

0774xx B     Branch

Line 7 of the diagram of 16-bit short instructions shows how condition values that are invalid result instead in an additional category of instructions which affect the flags used for predicated instructions.

0700xx CTF   Condition to Flag       Set flag to 1 if condition valid; set flag to 0 if condition not met

0760xx SFC   Set Flag on Condition   Set flag to 1 if condition met; leave it unaffected otherwise
0764xx CFC   Clear Flag on Condition Set flag to 0 if condition met; leave it unaffected otherwise

This instruction may manipulate 16 flags; although the header format may only employ eight of them, there are also jump on flag instructions.


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