The formats of the basic 32-bit instructions for this architecture are shown in the three diagrams below:
First, the instructions that are 32 bits in length which can never affect the condition code bits, as they perform functions such as load and store, or jump are as follows:
In order to allow room in the opcode space for pairs of 16-bit instructions to also occupy an instruction slot, the base register field for basic memory-reference instructions with a 16-bit displacement has been shortened from three bits to two.
Important Note: the registers that may be used as base registers, in this case, with 16-bit displacements are registers 29, 30, and 31, not registers 25, 26, and 27.
Note that the Subroutine Jump instruction in line 14 has an
offset field. Normally, this field will contain 000.
If it contains a nonzero value, then, instead of the return address pointing to
the memory location immediately following the end of the instruction, it will
have the offset, multiplied by 4, added to it. This allows returning from a
subroutine to be more efficient when the subroutine call instruction is the last one in a block;
the header of the next block, and any instruction slots which are not decoded
in order to contain pseudo-immediate values, will be skipped without having to
be first recognized and processed.
The offset field is in units of four bytes, or 32 bits, so this may not be used to cover cases where the unused space is an odd multiple of 16 bits.
While the conditional jump instructions, like the subroutine jump instructions, have a 16 bit displacement and a base register field, have the full complement of addressing modes, even if they are not shown on the diagram, and thus the conditional jump instructions may have nine-bit relative displacements, in line 10 of the diagram there is still also provided a 32-bit version of the conditional branch instructions, such as are included among the 16-bit instructions.
However, these have a ccset field, which allows them to be used with one of seven possible alternate sets of condition code bits, in addition to the normal set of condition code bits, selected when the bits in this field are all ones.
This is chosen so that the normal carry bit can be the leftmost bit in the register containing the program status word, the leftmost part of which is all the condition codes.
The 32-bit version of the set flag instruction, an instruction that is also found among the 16-bit instructions, also includes this field.
Following these instructions, there are the instructions that are 32 bits long which perform
arithmetic operations, and so have a C bit which will be set to 1
if the instruction is to affect the condition code bits:
Note that in lines 4 and 5 of the diagram, there is a second set of two-address register-to-register operate instructions for which a more limited set of possible opcodes is available which allow the alternate condition code bits to be set instead of the primary set of condition code bits.
Provision has been made for allowing a three-bit decode field, which allows space to be reserved for pseudo-immediate operands for operate instructions, to be specified at the start of a block while minimizing the overhead required for this.
The decode field contains one less than the number of the eight
instruction slots in the block, including the first one which may be a header, that
are to be decoded. Thus, if one 32-bit instruction slot at the end of the current block
is to be reserved for a pseudo-immediate value, it will contain the value 6, or
110 in binary.
The position field indicates the position in the block where the instruction in the first instruction slot is to be considered to be placed for purposes of the sequence of execution.
If the position field contains one, then the instructions in the block will be executed in sequence. If it contains a two, then the contents of the second instruction slot will be executed first, then the register-to-register operate instruction in the first instruction slot, and then the remaining instructions in the block. And so on; the position field identifies the instruction slot in the block, from the second slot (number one, as the count starts from zero, as addresses do) before which the instruction is to be executed. The value zero is not normally used in the standard case.
In this way, as it is a two-address register-to-register operate instruction that calls for a pseudo-immediate value, a compiler need not modify the sequence of generated instructions to reserve space for a header, as in either case, whether that instruction is a normal one, or one that uses an alternate condition code set, the opcode field is exactly the same length.
This scheme, as described so far, cannot completely cover any arbitrary ordering of instructions; the compiler might generate an instruction requiring a pseudo-immediate that falls near the end of the block; in which case, padding to move it to an early spot in the next block is required. But non-trivial manipulations of the generated code are already avoided.
However, this case is also addresed. Note that the pImm field in the instruction formats shown is only four bits long. This is sufficient for a pointer to any aligned 16-bit halfword within a block. A byte pointer is not required, as there is a format for immediate values of one byte in length, and all other data types longer than 8 bits are a multiple of 16 bits in length.
This has made room for a bit in the instruction marked D, the deferred bit.
If this bit is set, then the value in the position field refers to an instruction slot in the block following the current block. Therefore, if, in a generated sequence of instructions, an instruction with a pseudo-immediate value would be inserted after the instructions already placed in a block being prepared, and then leaving insufficient remaining space for the pseudo-immediate value, instead, the pseudo-immediate value can be placed within that block, and as many instructions as needed can be postponed until the next block.
Pathological cases are still possible where padding with empty space is required. One of the instructions that might be needed to be moved to the next block might be an instruction which already had a pseudo-immediate value that was present in the block. Then that instruction, not in this header format, would be separated from the value it required. In that case, since the block in its prior state contained a pseudo-immediate value, a decode field was already present, and so the required padding could be achieved simply by reserving empty space with the decode field, rather than potentially consuming cycles by inserting no-operation instructions into the instruction stream.
Note that including a D bit in ordinary, non-header operate instructions which refer to pseudo-immediate values, and, since they don't include a position field, defining it to indicate the pointer is to a pseudo-immediate value in the previous block, the contents of which the computer would have to retain after the instructions in the block were executed, an option which may suggest itself, would still not fully take care of all possible pathological cases, as now the preceding block would not necessarily contain an instruction with a pseudo-immediate value, and therefore it would not necessarily have a decode field present, unless a header were added, to allow for a pseudo-immediate value for use with the next block to be placed there.
It should be noted that the position field in a header of this form moves the operation performed by the instruction, not the text of the instruction. This distinction is significant, as it aids in understanding cases like the following:
As, for example, the header field calling for 34-bit instructions contains a decode field, the fact that the result of placing a header of this form before such a header could be well-defined, based on the principle that the decode field moves the operation performed by an instruction, not the text of the instruction, it is never necessary to do this.
The purpose of this type of header is to eliminate the overhead of a header for indicating a decode field. As all other headers already contain a decode field, it is never necessary to combine this type of header with any other type of header.
There are also special instruction formats, which make additional instructions available, that may be indicated by means of fields in a header block which indicate which individual instruction slots in a block contain an instruction in one of these special formats.
It is possible to specify an alternate field in the header. This is used to allow 32-bit memory-reference instructions with the normal available complement of registers to be placed within a block where the default instruction format is changed to one allowing pairs of 16-bit instructions, and so the memory-reference instructions are modified so as to be restricted in some of the addressing modes they may use, as well as a form of the multiple-register instructions with a limited capability of being indexed. The format of these instructions is shown below:
And then, this diagram
shows the format of the memory-reference instructions when modified by the fourth type of special header which adds load and store memory-reference instructions operating on the extended register banks.
The instructions are shown in the diagram as 35 bits long.
The first bit, the B or break bit, is not present for the first of the seven instructions in a block, since simultaneous execution does not cross block boundaries.
The following two bits are in the prefix field corresponding to the instruction in the 32-bit block header.
It is only the rightmost 32 bits of the 35-bit instruction which are contained in its 32-bit instruction slot.
Therefore, it is still possible for a decode field to be used in conjunction with instructions of this format, so that they can reference pseudo-immediate values.
The operate instructions are modified as shown in the following diagram:
This allows these instructions to fit in the opcode space, despite the normal load and store memory-reference instructions in lines 6 through 10 of the previous diagram which use the normal 32-register register banks being modified so as to use all seven possible base registers with 16-bit displacements.
Finally, this diagram
shows the format of pseudo-operations, selected by setting the P bit in the header for the 35-bit instructions.
Note that these instructions have the form of a memory-reference instruction.
The first action of such an instruction is to place the effective address of the instruction in arithmetic/index register 1.
Note that this means that register 1 is not useful as an index register for these
instructions. Therefore, if the Source Index (sX) field contains
001, instead of specifying indexing with arithmetic/index register 1,
it specifies indirect addressing.
Then, the instruction causes a subroutine jump.
The target address for the subroutine jump is found as follows:
The seven-bit value in the Opcode field of the instruction is shifted left three places, to form a displacement in units of 64 bits;
This is added to the value contained in arithmetic/index register 16, and the result is used as a pointer into a table of the addresses of the routines to perform the various pseudo-operations.
The return address for the subroutine is stored in arithmetic/index register 12.
Note that the Destination Register (dR) field in the instruction is not automatically processed, and must be manually interpreted by the pseudo-operation routine if desired.
Full format 32-bit memory-reference instructions, where all seven possible base registers, rather than only three of them, may be used with 16-bit displacements, have the following form:
In this instruction format, the operate instructions have the following form:
This instruction format is available in two cases:
Note that the format of these instructions is very similar to that of 35-bit instructions, except the additional instructions using banks of 128 registers are not included.
Also, there is a header type for 34-bit instructions. These are very similar to the 35-bit instructions, but with two important differences.
The first is the absence of the break bit as a part of every instruction.
The second is that, instead of adding a new set of memory-reference instructions that work with banks of 128 registers, other extensions to the instruction set are provided.
In the case where the type bits in the header indicating
that 34-bit instructions are used in the block are 00,
the new memory-reference
instructions added are ones that work with additional data types. Since the
architecture provides a very large opcode space for operate instructions,
it is only reasonable to suspect that some of those operate instructions will
support new data types, and some of those new data types will be such as to
have specialized internal forms for computation, which means they will
require their own load and store instructions.
Having the option of expanding this one part of the instruction set, the memory-reference instructions, that is very limited allows this to be dealt with without the double overhead of both using a header to indicate 48-bit and 64-bit instructions may be present, and then using such long instructions for this function.
The memory-reference instructions of this type have this form:
and the operate instructions of this type have this form:
In the case where the type bits in the header indicating
that 34-bit instructions are used in the block are 01,
the new memory-reference instructions added are ones that perform
arithmetic operations, extending the instruction set to be CISC-like
instead of a load-store architecture.
To allow room for a C bit, indicating that these additional instructions may set the condition code bits, the size of the base register field for these instructions for 16-bit displacements is reduced to two bits from three. As with the memory-reference instructions in the standard form of the instruction set, the registers that this field may reference as base registers are integer registers 29, 30, and 31.
In this case, the form of the memory-reference instructions is:
and that of the operate instructions is the same as for the other option.