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Instruction Format

The formats of the basic 32-bit instructions for this architecture are shown in the three diagrams below:

First, the instructions that are 32 bits in length which can never affect the condition code bits, as they perform functions such as load and store, or jump are as follows:

In order to both allow the basic memory-reference instructions shown in the first five lines of the diagram to be indexed, and to act on unaligned operands, both of which things are required to allow the full complement of addressing modes to be available with them, some compromises had to be made. Only registers 1, 2, and 3 can be used as index registers with these instructions, and only registers 25, 26, and 27 can be used as base registers with 16-bit displacements with these instructions.

Note that the Subroutine Jump instructions have an offset field. Normally, this field will contain 000. If it contains a nonzero value, then, instead of the return address pointing to the memory location immediately following the end of the instruction, it will have the offset, multiplied by 4, added to it. This allows returning from a subroutine to be more efficient when the subroutine call instruction is the last one in a block; the header of the next block, and any instruction slots which are not decoded in order to contain pseudo-immediate values, will be skipped without having to be first recognized and processed.

Second, the instructions that are 32 bits long which perform arithmetic operations, and so have a C bit which will be set to 1 if the instruction is to affect the condition code bits:

In addition, other instructions of this form are shown in the diagram below:

This diagram shows a shortened set of basic instructions, both operate instructions in lines 1 through 5, and memory-reference instructions in lines 6 through 25, which also contain a decode field. This allows space reserved for pseudo-immediate values to be indicated without the need to reserve an entire 32-bit instruction slot for that purpose.

Instructions in this format, shortened to make room for a decode field, as shown in this diagram may appear anywhere in a block. However, the decode field will cause instruction slots to be reserved only if the short format instruction is in the first 32-bit instruction slot of the block. (Since all possible formats for a 32-bit block header include a decode field, there is no need to make provision for having a short format instruction following a header.)


Also, it is possible to specify an alternate field in the header field. This is used to allow 32-bit memory-reference instructions with the normal available complement of registers to be placed within a block, as well as a form of the multiple-register instructions with a limited capability of being indexed. The format of these instructions is shown below:


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