This page deals with three forms of shorter instructions.

16-bit instructions are an intrinsic part of the main instruction set; in the absence of a header, a 32-bit instruction slot may contain a pair of 16-bit instructions instead of a single 32-bit instruction. Some types of headers modify how 16-bit instructions may appear in the program code in the block it begins.

Compound instructions and 8-bit instructions, on the other hand, are associated with two special types of header, and do not occur in program code in the absence of those specific headers. This is also true of the 16-bit memory-reference instructions also described on this page.

The instructions to be described in this section have the formats shown in the upper left corner of this diagram:

The 16-bit instructions do not include memory-reference instructions, or the subroutine jump instruction. However, while the set of 16-bit instructions is therefore not complete in itself, it is sufficient that a large proportion of the instructions in a program could be 16-bit instructions.

The register-to-register operate instructions within this group of instructions, as shown in line 1 of the first numbered sequence of lines in the diagram, contain a two bit page field, followed by a three-bit destination register field, and a three bit source register field. The five-bit value from 0 to 31 which indicates the destination register is formed by concatenating the page field and the destination register field, and that which indicates the source register field is similarly formed by concatenating the page field and the source register field.

In this way, even when 16-bit instructions are used, four threads of calculation, each using a different group of eight registers, can be interleaved in a sequence of code, allowing more instructions to execute either simultaneously or in rapid succession before a dependency is encountered.

Line 1 gives the format of the operate instructions. Integer instructions reference the integer registers, and floating-point instructions reference the floating-point registers, as might be expected.

There are 96 possible opcodes, as the first two bits of an opcode may not be both 1, as these combinations are reserved for other 16-bit instructions.

The opcodes (with the first four bits appearing along the top of the chart, and the last three bits appearing on the right) are:

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 SWB IB SWH IH SW I SWL SWM SWF SWD SWQ 000 CB CH C CL CM CF CD CQ 001 LB ULB LH ULH L UL LL LM LF LD LQ 010 STB XB STH XH ST X STL XL STM STF STD STQ 011 AB NB AH NH A N AL NL AM AF AD AQ 100 SB OB SH OH S O SL OL SM SF SD SQ 101 MH MEH M ME ML MEL MM MF MD MQ 110 DH DEH D DE DL DEL DM DF DD DQ 111

The different instructions are:

For integer types:

M MULTIPLY Multiply the contents of the source and destination locations, placing the least significant part of the result of the same length as the two input operands in the destination location, with sign extension if that is shorter than the length of the destination register D DIVIDE Divide the contents of the source location by the contents of the destination location, placing the quotient in the destination location L LOAD Place the contents of the source operand in the destination register; if the type involved is smaller than the register, perform sign extension ST STORE Fill the destination location from the least significant part of the source location A ADD Add the contents of the source and destination locations, placing the result in the destination location S SUBTRACT Subtract the contents of the source location from those of the destination location, placing the result in the source location SW SWAP Exchange the contents of the source and destination locations C COMPARE Subtract the contents of the source location from the contents of the destination location, but with the operation modified so that overflow cannot possibly result, and set the condition codes appropriately without modifying the destination location I INSERT Fill the least significant bits of the destination register with the contents of the source location, leaving the rest of the destination register unaffected UL UNSIGNED LOAD Fill the least significant bits of the destination register with the contents of the source location, and clear the remaining more significant bits of the destination register X EXCLUSIVE OR Perform a bitwise Exclusive OR operation between the contents of the source and destination locations, placing the result in the desination location N AND Perform a bitwise Logical AND operation between the contents of the source and destination locations, placing the result in the desination location O OR Perform a bitwise Logical OR operation between the contents of the source and destination locations, placing the result in the desination location ME MULTIPLY EXTENSIBLY Multiply the contents of the source and destination locations. Take the full product, as an integer having twice the size as that of the source and the destination, and: - in the case of the halfword and integer versions of the instruction, place it in the destination register, with sign extension in the halfword version; - in the case of the long version of the instruction, place the most significannt half of the result in the destination register, which must be an even-numbered register, and place the least significant half of the result in the register following DE DIVIDE EXTENSIBLY Divide a destination operand of twice the length of that indicated by the instruction type (and located as the result of the MULTIPLY EXTENSIBLY instruction) by the source operand; store the double length quotient in the destination location (again following the MULTIPLY EXTENSIBLY result placement) and the single length remainder in the next register following those that are used. Whenever a result is not wide enough to fill a register, sign extension is performed. Division is performed giving a result as if both operands were converted to positive numbers before starting, with the signs then set afterwards to give a correct result based on the actual signs of the operands. Thus both the quotient and the remainder will be positive or zero if the dividend and divisor have the same sign, and both will be negative or zero if they are of opposite signs.

The possible integer types, and the suffixes that indicate them, are:

B BYTE An 8-bit two's complement integer H HALFWORD A 16-bit two's complement integer INTEGER A 32-bit two's complement integer L LONG A 64-bit two's complement integer

The integer registers are 64 bits long, to contain the longest of these types.

The available floating-point operations are SWAP, LOAD, STORE, ADD, SUBTRACT, MULTIPLY, and DIVIDE. Their functions are basically the same as those of the corresponding integer operations, except that floating-point arithmetic is performed.

The possible floating-point types for 16-bit instructions, and the suffixes that indicate them, are:

M MEDIUM A 48-bit floating-point number (preferably aligned on 16-bit boundaries) F FLOATING A 32-bit floating-point number D DOUBLE A 64-bit floating-point number Q QUAD A 128-bit floating-point number

with their formats as indicated within this diagram:

These instructions are then also suffixed RC for Register Compact to indicate the addressing mode.

Lines 2 through 5 of the diagram illustrate the shift and rotate short instructions. These are:

060xxx LSLLC Logical Shift Left Long Compact 061xxx LSRLC Logical Shift Right Long Compact 062xxx RLLC Rotate Left Long Compact 063xxx ASRLC Arithmetic Shift Right Long Compact 0640xx LSLC Logical Shift Left Compact 0650xx LSRC Logical Shift Right Compact 0660xx RLC Rotate Left Compact 0670xx ASRC Arithmetic Shift Right Compact 0644xx LSLHC Logical Shift Left Halfword Compact 0654xx LSRHC Logical Shift Right Halfword Compact 0664xx RLHC Rotate Left Halfword Compact 0674xx ASRHC Arithmetic Shift Right Halfword Compact 0646xx LSLBC Logical Shift Left Byte Compact 0656xx LSRBC Logical Shift Right Byte Compact 0666xx RLBC Rotate Left Byte Compact 0676xx ASRBC Arithmetic Shift Right Byte Compact

Logical right and left shifts insert zeroes; the arithmetic right shift inserts a copy of the existing value of the most significant bit into the leftmost position of the word so as to maintain the sign as either negative or non-negative.

An arithmetic left shift inserts zeroes into the leftmost end of a number regardless of its sign, just like a logical left shift, but it differs in that the overflow bit is set if a left shift results in a change of the sign of the value being shifted, instead of merely a carry out of that value; this difference is, however, not applicable to short instructions, as they may not alter the condition codes, not having space for a C bit.

In the 16-bit short instructions, there is no available separate region of opcode space for the rotate instructions, and so instead the arithmetic left shift is replaced by rotate left.

Line 6 of the diagram shows the branch instructions.

The displacement is an 8-bit signed value, in two's complement form, which may vary from
-128 to +127. The displacement is in units of 16 bits. No attempt is made to skip over values
corresponding to the 32-bit instruction slots containing header information in counting; the
displacement is an actual displacement in terms of the memory address, not a count of skipped
instructions. A displacement of zero refers to the position immediately following the
instruction. The target of a branch instruction *must* always be an actual executable
instruction, and not a setup directive, an immediate value, or any part of a 48-bit or 80-bit
instruction other than its first 16 bits.

The available branch instructions are:

16 bit 0704xx BL Branch if Low 0710xx BE Branch if Equal 0714xx BLE Branch if Low or Equal 0720xx BH Branch if High 0724xx BNE Branch if Not Equal 0730xx BHE Branch if High or Equal 0734xx BNV Branch if No Overflow 0740xx BV Branch if Overflow 0750xx BC Branch if Carry 0754xx BNC Branch if No Carry 0774xx B Branch

Line 7 of the diagram of 16-bit short instructions shows how condition values that are invalid result instead in an additional category of instructions which affect the flags used for predicated instructions.

0700xx CTF Condition to Flag Set flag to 1 if condition valid; set flag to 0 if condition not met 0760xx SFC Set Flag on Condition Set flag to 1 if condition met; leave it unaffected otherwise 0764xx CFC Clear Flag on Condition Set flag to 0 if condition met; leave it unaffected otherwise

Line 8 of the diagram of 16-bit short instructions shows how an additional invalid condition value provides another special instruction:

0770xx SVC Supervisor Call

This instruction performs the equivalent of an interrupt from within software, allowing portions of the operating system not running in supervisor state to request services from the kernel, as well as possibly also allowing user programs to request services from the operating system.

The eight formats of 16-bit instructions occur within 32-bit instruction slot the
contents of which begin with `0`

. Above those formats is shown the format of
an instruction slot that contains two 16-bit instructions; both halves of the instruction
slot contain a zero as their first bit.

The header of an instruction block may indicate alternate forms of 16-bit instructions.

A **dual-16** short header clause has bits which indicate instruction slots
which always contain two 16-bit instructions. Instead of the first bit of a 16-bit instruction
bit always being 0, it now functions as a C bit; if it is 1, the instruction is allowed to
affect the condition codes.

Also, there is a special header which indicates High Density Code (HDC). When that header
is applied, all instruction slots, by default, behave as if the dual-16 type is indicated for
them, but if the corresponding bit in the **memref** field is a 1, a 1 bit at
the beginning of a 16-bit instruction instead indicates that it is a memory-reference
instruction.

The 16-bit memory-reference instructions have one of two possible formats, only one of which is available for an entire instruction block. The two possible formats are illustrated in the diagram below:

When the format in the first line is used, then if the bit marked X is 1, the instruction is indexed by arithmetic/index register 1.

All memory-reference instructions in high-density code have register 0, either arithmetic/index register 0 or floating-point register 0, as appropriate, as their destination register.

In the first instruction format, the possible opcodes are:

00 IL Integer load 01 IST Integer store 10 FL Floating load 11 FST Floating store

In the second instruction format, the possible opcodes are:

000 SWA Swap 001 CMP Compare 010 LDA Load Accumulator 011 STR Store 100 ADD Add 101 SUB Subtract 110 MUL Multiply 111 DIV Divide

Of these instructions, only the **Compare** instruction
sets the condition code bits.

Thus, the choice made by the instruction format bit is between load-store instructions with indexing, and a choice between two operand types, or memory-reference instructions of only one type without indexing that can also do arithmetic.

If that bit is 0, the next four bits indicate which type is used for integer operands of memory-reference instructions, and which type is used for floating point operands of memory-reference instructions, as follows:

Integer type: 00 Byte 8 bits 01 Halfword 16 bits 10 Word 32 bits 11 Doubleword 64 bits Floating type: 00 Medium 48 bits 01 Single 32 bits 10 Double 64 bits 11 Extended 128 bits

If that bit is 1, the last three bits of the next four bits (the first of them must be 0) indicates the one type used for all operands of memory-reference instructions:

Integer types: 000 Byte 8 bits 001 Halfword 16 bits 010 Word 32 bits 011 Doubleword 64 bits Floating types: 100 Medium 48 bits 101 Single 32 bits 110 Double 64 bits 111 Extended 128 bits

One of the types of short header clause provides seven bits with which to indicate the instruction slots which contain compound instructions.

These permit operations to be specified in a compact manner.

The form of an instruction slot containing a compound instruction is as follows:

Four bits, which indicate if that slot contains the first part, the last part, a middle part, or the only part of a single compound instruction, and

Eight fields, each seven bits long, that contain the actual components of the compound instruction.

The syntax of a compound instruction is basically that of stack-oriented computing. It is expected, however, that compound instructions will only be implemented by means of a stack in the smallest implementations of the architecture, and will instead by implemented by means of operator forwarding in larger pipelined implementations.

Compound instructions only deal with floating-point data types.

The first four bits in the instruction slot have the form:

First two bits: 00 Only part of one complete compound instruction. 01 First part of a longer compound instruction. 10 Neither the first nor the last part of a longer compound instruction. 11 Last part of a longer compound instruction. Last two bits: 00 Medium 48 bits 01 Floating 32 bits 10 Double 64 bits 11 Extended 128 bits

The seven-bit steps in a compound instruction have the form:

00 followed by a register number: push the number in that register on the stack.

010 - an operator which takes the two top numbers on the stack, removes them, performs an operation, and places the result on the stack. The instructions of this form are:

010 0000 Add 010 0001 Subtract the number on the top of the stack is subtracted from the number below it 010 0010 Multiply 010 0011 Divide the second number from the top of the stack is divided by the number on the top of the stack 010 0100 Power the second number from the top of the stack is raised to the power specified by the number on the top of the stack 010 0101 Root the n-th root of the second number from the top of the stack is taken, where n is the number on the top of the stack 010 0110 Atan2 The FORTRAN function ATAN2(x,y) where y is the number on the top of the stack, and x is the second number from the top of the stack 010 0111 Radius The square root of the sum of the squares of the top two numbers on the stack

011 - a stack operation. The instructions of this form are:

011 0000 Swap The top two numbers on the stack are exchanged. 011 0001 Dup An extra copy of the top number on the stack is added to the top of the stack. 011 0010 Rot The third value down in the stack is removed from that spot, and added to the top of the stack. 011 0011 Over A copy of the second value down in the stack is added to the top of the stack.

Also, in this group, the code 011 1111 is used to fill all unused seven-bit spaces for steps after the end of a compound instruction.

10 - a single-operand function. The instructions of this form are:

10 00000 Minus The additive inverse of the top value on the stack, or minus one times it, or zero minus it, replaces the top value on the stack 10 00001 Reciprocal 10 00010 Square root 10 00011 Square 10 00100 Sine The top value on the stack is replaced by its sine, where that value is considered to be in radians 10 00101 Cosine 10 00110 Tangent 10 00111 Cotangent 10 01000 Log The top value on the stack is replaced by its natural logarithm 10 01001 Exp

11 followed by a register number: pop the top value on the stack, and store it in that register.

Eight bit instructions have the form of memory-reference instructions, but they specify operations between register zero, as the destination register, and one of the other registers, as the source register.

The first three bits are the opcode, the remaining five bits are the source register. The possible operations are:

000 SWA Swap 001 CMP Compare 010 LDA Load Accumulator 011 STR Store 100 ADD Add 101 SUB Subtract 110 MUL Multiply 111 DIV Divide