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The Concertina II Architecture

This is now my fifth attempt to propose a successor to my original Concertina architecture, intended to be simple and straightforward enough to have a chance of gaining interest and acceptance.

The basic complement of registers is as follows:

There is a bank of 32 fixed-point registers; each one is 64 bits wide, since that is the maximum length used. As well, there is another bank of 32 floating-point registers, each one 128 bits wide so as to be able to accomodate extended-precision numbers.

There are also banks of 128 fixed-point registers and 128 floating-point registers; these are for the use of instructions that execute without using interlocks that check for whether preceding instructions that modify the contents of registers they take data from have finished. Instead, those instructions contain bits by which they explicitly indicate which instructions they are dependent upon, thus functioning in the fashion associated with Digital Signal Processor (DSP) chips.

Four sets of eight base registers are provided separately from the arithmetic-index registers; as the contents of these registers are normally static, this both keeps the arithmetic-index registers available for calculations and maintains the compactness of instruction formats. The first set of eight base registers is used in jump and jump to subroutine instructions, and the same eight registers are used for those instructions regardless of the size of the segment implied by the instruction format. The other three sets of base registers are used for all other memory-reference instructions. The second set of eight base registers, the short base registers, is used to point to segments that are 4,096 bytes in length; the third set of eight base registers, the long base registers, is used to point to segments that are 65,536 bytes in length, and the fourth set of base registers, the extended base registers, is used to point to segments that are 1,048,576 bytes in length.

Many instructions have a three-bit index register field.

Sixteen-bit register-to-register instructions are provided, which conserve opcode space by dividing the thirty-two registers in both the integer and floating-point banks into four groups of eight registers, with the intention of allowing four instruction sequences, each using eight of the registers, to be interleaved in order to assist with efficient instruction pipelining.

A similar principle is used with the index register field; the meaning of the index register field may be determined by the destination register field of the instruction, so that a register from the same group of eight registers as the destination register is used as the index register.

However, it may be more appropriate for an index register to be shared among the subthreads of a calculation instead of being local to each one, so some values instead always refer to a register in the first group of eight arithmetic-index registers.

Thus, the index register field is to be interpreted as follows:

Field   Register used for indexing

  0     No indexing
  1      1
  2      2
  3      3
  4      4/12/20/28
  5      5/13/21/29
  6      6/14/22/30
  7      7/15/23/31

The short vector registers are 256 bits wide. There are sixteen such registers.

There are 64 long vector registers; each long vector register will contain 64 entries. These entries will be 128 bits long.

The instruction formats are as shown below:

The floating-point formats intended for regular use that are supported by the architecture are as shown below:

In addition, as will be described in a later section, Decimal Floating Point is supported, as is the Compatible floating-point format, which corresponds to that used in certain popular mainframe computers.

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