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The Concertina II Architecture

This is now my eighth attempt to propose a successor to my original Concertina architecture. I hope that finally this time I have found a way to achieve the goals I have set for myself while avoiding excessive complexity.

In this architecture, there are seven modes of operation, with three significantly different instruction formats: 16-bit mode, 16-bit mode with extended addressing, 32-bit mode, 32-bit mode with 64-bit addressing, compatible 64-bit mode, standard 64-bit mode, and special mode.

The available registers depend on the mode in use; those available in 16-bit mode are a subset of those available in 32-bit mode, and in turn those available in 32-bit mode are a subset of those available in 64-bit mode.

The overall register set is illustrated in the following two diagrams:

Registers, or portions of registers, shown in white are available in all modes.

Registers, or portions of registers, shown in yellow are available in all modes except 16-bit mode; they are available in 16-bit mode with extended addressing. It is the four 24-bit base registers that are available in 16-bit mode with extended addressing, but not plain 16-bit mode which are shown in this color.

Registers, or portions of registers, shown in orange are available in both forms of 64-bit mode and 32-bit mode, but not in either form of 16-bit mode.

Registers, or portions of registers, shown in green are available in 32-bit mode with 64-bit addressing, compatible 64-bit mode and standard 64-bit mode. The most significant 32 bits of the base registers and short base registers are the ones shown in this color, as they are the ones required for 64-bit virtual addresses.

Registers, or portions of registers, shown in light blue-green (cyan) are available in both compatible 64-bit mode and standard 64-bit mode only. The most significant 32 bits of the arithmetic-index registers, and the components of first eight integer long vector registers are the ones shown in green, as the only difference between 32-bit mode with 64-bit addressing and compatible 64-bit mode is that these registers are expanded to 64 bits in compatible 64-bit mode.

Registers, or portions of registers, shown in light brown are only available in standard 64-bit mode.

Thus, in 16-bit mode, only the registers or portions thereof shown in white are available.

In 16-bit mode with extended addressing, the registers or portions thereof shown in white or in yellow are available.

The register complement available in 32-bit mode consists of what is shown either in white, in yellow, or in orange.

In 32-bit mode with 64-bit addressing, the available register complement is that which is shown in either white, yellow, orange, or green.

In compatible 64-bit mode, that which is shown in any color except grey: that which is white, yellow, orange, green, or light blue-green is available.

In standard 64-bit mode everything present in the diagram is available.


Thus, in 16-bit mode, there are eight 32-bit arithmetic registers, and eight 80-bit floating-point registers.

In 16-bit mode with extended addressing, there are eight 32-bit arithmetic registers, eight 80-bit floating-point registers, and four 24-bit base registers.

In 32-bit mode, there are eight 32-bit arithmetic registers, eight 128-bit floating-point registers, eight 32-bit base registers, eight 32-bit short base registers, and sixteen 256-bit short vector registers, as well as eight integer long vector registers, each consisting of sixty-four 32-bit entries, and eight floating-point long vector registers, each consisting of sixty-four 128-bit entries.

In 32-bit mode with 64-bit addressing, there are eight 32-bit arithmetic registers, eight 128-bit floating-point registers, eight 64-bit base registers, eight 64-bit short base registers, and sixteen 256-bit short vector registers, as well as eight integer long vector registers, each consisting of sixty-four 32-bit entries, and eight floating-point long vector registers, each consisting of sixty-four 128-bit entries.

In compatible 64-bit mode, there are eight 64-bit arithmetic registers, eight 128-bit floating-point registers, eight 64-bit base registers, eight 64-bit short base registers, and sixteen 256-bit short vector registers, as well as eight integer long vector registers, each consisting of sixty-four 64-bit entries, and eight floating-point long vector registers, each consisting of sixty-four 128-bit entries.

In standard 64-bit mode, there are thirty-two 64-bit arithmetic registers, thirty-two 128-bit floating-point registers, eight 64-bit base registers, eight 64-bit short base registers, and sixteen 256-bit short vector registers, as well as sixty-four integer long vector registers, each consisting of sixty-four 64-bit entries, and sixty-four floating-point long vector registers, each consisting of sixty-four 128-bit entries.


The basic instruction formats available in 16-bit mode with extended addressing are:

In plain 16-bit mode, the instruction formats are the same, except that 16-bit address constants simply consist of a 16-bit absolute address instead of a two-bit base register field and a 14-bit displacement field.

Note that 16-bit mode still allows operations on 32-bit integers and on both 32-bit and 64-bit floating-point numbers, thus, although the instruction format is similar to that of some classic minicomputers, it is providing at least a basic mainframe capability.


The basic instruction formats available in 32-bit mode, 32-bit mode with 64-bit addressing, and compatible 64-bit mode are:

In compatible 64-bit mode, the only thing that changes is that the base registers are now 64 bits long, and so a larger virtual memory can be accessed. Even the arithmetic-index registers remain 32 bits long, limiting the size of arrays that can be addressed.

Long integer operations on 64-bit operands are available in 32-bit mode and compatible 64-bit mode. For these instructions, the destination register (and the source register, if the instruction is register-to-register) must be an even-numbered register, as these instructions now operate on pairs of registers.

In this diagram, address constants for instructions using the short base registers are only shown in the form they have when their first bit is a 1. The first bit is followed by a three-bit base register field, specifying one of the short base registers, and then a twelve-bit displacement.

If, instead, the first bit is a 0, the remainder of the address is a fifteen-bit displacement, which is added to the contents of short base register zero to form the effective address.

When the first bit is a 1, and the base register field consists of all zeroes, this is used to indicate Array Mode. In Array Mode, the twelve-bit displacement is shifted either two bits left (in 32-bit mode) or three bits left (in compatible 64-bit mode) and added to the contents of short base register one, to form an indirect address. This points to an address value, either 32 bits or 64 bits in length, as is appropriate to the addressing mode, which in turn points to the operand of the instruction. This allows a program to access a large number of large arrays without having to reload base registers with pointers to those arrays in order to access them.

Since a base register field of zero, in some of the instructions using the normal base registers, is used to indicate register-to-register instructions, Array Mode is only available with the short base registers.


The basic instruction formats available in standard 64-bit mode have the form:

The form of instruction set available in 64-bit mode is organized so that program code may be fetched in 256-bit blocks, and the block is divided into 32-bit instruction words which may be decoded in parallel. After decoding, the instructions will still be executed in series.

Instructions longer than 32 bits are provided, but each 32-bit portion of the instuction is formatted so that it can be decoded independently.

One exception to the principle of separate decoding is permitted, under conditions that will not cause delays. The last instruction of a 256-bit instruction block, or any group of consecutive instructions which include the last instruction, may have an immediate operand that is a multiple of 32 bits in length. These immediate operands will then begin the next instruction block; as that will be fetched in a subsequent cycle, this makes use of an inherently serial situation. It is intended that if the immediate operands extend for more than 256 bits this is to be fully supported.


A 32-bit instruction word may be composed of two 16-bit instructions. This instruction format is illustrated by line 1 of the diagram.

In addition to the first two bits of the word being 11, the first two bits of the opcode field must not be both 1. If they are not both 1, the dR and sR fields will be checked; they must not both be the same: if they are the same when the first two bits of the opcode field are not both 1, the instruction word will instead indicate an instruction of several specialized types.

The second half of that instruction word is another 16-bit short instruction if its first two bits are zero. (If the second instruction has the first two opcode bits both one, or its destination and source registers the same, it may be a specialized 16-bit instruction; these are reserved for future expansion.)

Also, as there was room for a 7-bit opcode field, with the restriction that its first two bits not be zero, even after including a condition code bit in the instruction format, 16-bit operate instructions are allowed to affect the condition codes. However, it is not useful for both operate instructions in a 32-bit instruction word to change the condition codes. Therefore, instead, if both condition codes are set, the instruction word is instead indicated to consist of two 16-bit instructions, neither of which may alter the condition codes, taken from a set of additional instructions for specialized operations such as register BCD arithmetic; this instruction format is shown in Line 2 of the diagram.

An instruction word may consist of a valid 16-bit short instruction in its first half, and something else in its second half, as well.

One example of this is shown in line 3 of the diagram. The first three bits of the second half of the word are 000. This ensures the two bits following the initial 00 are not both 1, so decoding of a 16-bit instruction continues. But the source and destination registers of the instruction in the second half of the world are both indicated as register 0, which is invalid; instead, the seven bits following the initial 000 are used as a seven-bit prefix to the following instruction. Since this instruction word type may be decoded independently of anything which precedes it, the decoding of the following instruction word isn't required to wait for the decoding of all previous words in the block to check for the presence of a prefix, which is why this instruction extension mechanism doesn't violate the principle of independent decoding.


However, there is one important restriction to be noted: because of the existence of prefixes, when branching into a block where the first several 32-bit instruction words are instead used for immediate data from instructions in the preceding block, it is possible that the immediate data might resemble an instruction word type that provides a prefix, causing incorrect decoding of the first instruction in such a block. Therefore, the first actual instruction in a block starting with immediate data may not be a branch target from outside the block.

Next, we will look at memory-reference instructions.

Line 4 of the diagram shows another instruction prefix format; this one provides a 12-bit prefix (thus, it is large enough to possibly include additional fields indicating registers). The same note concerning decoding applies to this format.

As a consequence of this, Only one prefix, either of this type or of the preceding type, may be applied to any one instruction. If two instruction words indicating prefixes appear, the prefix indicated in the first one will apply to the 16-bit instruction in the first half of the second instruction word, not to the instruction following both.

Lines 5 through 10 of the diagram show that when a 16-bit instruction, indicated by the first two bits of the instruction word being 11, is followed by a second 16-bit half beginning with 01, then the instruction word also contains two 16-bit instructions, but this time the second one is of an alternate type, either a 16-bit shift instruction, as shown in lines 5 through 8, or a 16-bit conditional relative branch instruction, as shown in line 9.

Also in this group is another prefix instruction; but this one does not provide a prefix for the next instruction; instead, it contains an 8-bit prefix for the next 256-bit block. Each bit in the prefix corresponds to one of the eight 32-bit instruction words in the block. There is also an opcode field, as there can be different prefixes of this type. In one case, each zero in the prefix field might indicate an instruction that can be performed in parallel with those that precede it. In another, each one in the prefix field might indicate an instruction word to be decoded in a completely different manner for a secondary instruction set.

Line 11 of the diagram shows the format of a multiple-register load and store instruction. These instructions must have a short-format memory address, and they cannot be indexed. They are distinguished from other memory-reference instructions by their opcodes.

Line 12 shows a standard memory-reference instruction with a long-format memory address, and Line 13 shows a standard memory-reference instruction with a short-format memory address.

Line 14 shows a standard memory-reference instruction that can access all 32 registers of the main integer and floating-point banks. These instructions also must use a short-format memory address.

Line 15 shows a three-address register-to-register instruction. The two opcode bits which precede the condition code bit must not be both one.

Line 16 shows the format of an instruction with a 16-bit immediate operand. The first two opcode bits must not be both one, because it is decoded as an instruction word beginning with a 16-bit instruction, only made invalid by the register field contents, which are only tested if the first two opcode bits do not, by being 11, indicate a different kind of instruction word.

Lines 17 and 18 show the format of a 48-bit long string or packed-decimal instruction. Both memory addresses in these instructins must be short format. The first word is distinguished from a word beginning with a 16-bit instruction by the two bits immediately following the first two bits also being both one; therefore, the last six bits are not tested for being two identical octal digits. The second word does contain a 16-bit instruction, to be executed before the string or packed decimal instruction: this is why that instruction only occupies 48 bits instead of 64 bits.

Lines 19 and 20 show the format of a 64-bit long string or packed decimal instruction. Only the format of instructions with long format memory addresses is shown, however, the addresses in these instructions may also be short format instead, in which case the corresponding base address fields in the instruction are instead available to indicate indexing for that memory operand.

Lines 21 through 23 indicate the 96-bit format for a three-operand string instruction; this allows separate source and destination operands for the Translate instruction.

Lines 24 through 29 show the formats of the three types of long vector instructions. Long vector instructions are similar in philosophy to the vector capabilities of vector supercomputers such as the Cray I and its successors.

Lines 30 through 35 show the formats of the three types of short vector instructions. Short vector instructions work by splitting a fixed-length long word into different numbers of parts, in this case, a 256-bit long word into two 128-bit floating-point numbers, four 64-bit floating-point numbers or long integers, eight 32-bit floating-point numbers or integers, sixteen short integers, or thirty-two bytes. Thus, they follow the philosophy of the vector instructions that are today common on most microprocessor architectures at this time.

Line 36 shows the format of a three-address register-to-register instruction that can access all 32 registers of the register banks.


In a memory-reference instruction, if the index register field contains a zero, this means that the address is not indexed, so arithmetic-index register 0 can only be used as an accumulator, and not an index register.

In instructions using the normal base registers, if the base register field contains a zero, on the other hand, it indicates Array Mode or the related Direct Mode. The first bit of the displacement field, if 0, indicates Array Mode, and if 1, indicates Direct Mode. In Array Mode, the contents of base register 0 are added to the value in the displacement field, shifted three places left, to provide the address of a 64-bit quantity in memory; this quantity, indexed as indicated in the instruction, is the effective address of the instruction.

Array Mode therefore allows a program to access multiple large arrays without having to use one base register for each array.

Direct Mode is only used with long integer instructions; here, the contents of base register 0 are added to the value in the displacement field, shifted three places left, to form the effective address of the instruction (which may also be indexed) to permit the array pointers used in Array Mode to be accessed and updated without the need to set two base registers to the same value.

In instructions using the short base registers, where the displacement field is twelve bits long instead of sixteen bits long, Array Mode is instead indicated as in 32-bit mode and compatible 64-bit mode: here, Array Mode uses short base register 1 instead of normal base register 0, and Direct Mode is not required as conventional addressing with base register 1 is also available.


There is also Special Mode.

This mode resembles the 16-bit modes in instruction format. However, the destination address in a standard instruction can only be a register, allowing more opcodes to be available.

Also, the register complement used in this mode does not belong to the sequence in which the other modes are arranged, in which each mode uses a proper subset of the registers used in the next more complex mode. Instead, the registers used in this mode are the ones shown in white in the diagram below:

While Special Mode is a 64-bit mode, because it is similar in structure to the 16-bit modes, it is intended to be used for programs that do not require a large portion of system program execution resources. Note the change in the format of the shift instructions.

Array Mode addressing is available in Special Mode.


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