The formats of the instructions for this architecture are shown in the diagram below:
The Long Vector Register and Long Vector Memory Progressive instructions may be of interest.
These instructions are intended to be employed in a loop handling a vector with more than 64 entries. The length of the total vector is placed into an integer register used as the length register prior to the start of the loop.
If the C bit is set in the instruction, the execution of the instruction is modified in addition to it being allowed to set the condition code bits: the instruction will decrement the contents of the length register by the number of elements in a vector register, which happens to be sixty-four.
It is intended that this will be done only for the last vector instruction in the loop. When the contents of the length register, prior to being decremented, are less than 64, they give a vector length for the instruction. Here, this applies to the register instructions as well.
If the I bit is set, which may be the case for most if not all of the memory-reference vector instructions in the loop, the selected index register (if, of course, indexing is also present) is incremented by the vector length times the operand element length (for example, eight if double-precision floats compose the operand), times the stride if one is present.
The intent is to facilitate writing loops to handle vectors of any length that are also independent of the number of elements in a vector register. However, vector instructions that involve more explicitly dealing with the vector registers, so that the code needs to be written around their size, seem to be necessary when it is desired to use a mask register to exclude some registers from certain operations.