Scratchpad mode is very similar to normal mode. In terms of the special instructons to be described in later sections, because it is almost identical in overall structure to normal mode, it is also identical in terms of which special instructions are available in that mode.
The format of the basic memory-reference instructions in this mode is:
The opcode space used in Normal Mode for memory-reference instructions performing arithmetic operations involving a memory location and one of the eight general registers or floating-point registers is now used for instructions that perform a load or store operation from the sixty-four supplementary registers of the appropriate type.
Also, a set of three-address register-to-register instructions is provided that are 32 bits in length, and which allow access to the base registers and the various types of scratchpad registers as well as the arithmetic-index registers, the floating-point registers, and the supplementary registers.
Thus, although there are instructions of different lengths, and many of the longer instructions still do not follow the load/store model, in this mode the processor has a full load/store instruction set similar to that of a RISC design, in addition to other non-RISC instructions.
These instructions have eight bits allocated to the opcode, divided between the first two halfwords of the instruction, but the first two bits of the opcode cannot both be 1. This allows these instructions to include additional opcodes for the instructions for the simple floating type, which will be discussed later.
In addition, since the fixed-point instructions of this group normally have the 64-bit supplementary registers as their destinations, a set of 32-bit integer instructions which use the high 32 bits of their destination register is provided. This is inspired by a similar feature recently added by IBM to its z/Architecture systems with the zEnterprise z196. It differs in that instructions working with the 8-bit or 16-bit types are not included, on the one hand, and, on the other, that multiplication and division instructions are added (but not the multiply extensibly and divide extensibly, which are more closely analogous to the multiply and divide instructions on the IBM 360 architecture).
One change to overall structure, which does not affect the availability of the various forms of additional instructions, is that the 16-bit instructions for moving data between the supplementary registers and the general registers, which begin with 010, were removed, and were replaced by the same compact set of memory-reference instructions for the general registers as used in local mode, although with their opcodes altered. This was felt to be reasonable, despite the fact that this mode emphasizes the scratchpad registers over the general registers, because without this change, the general registers would have been so isolated that the group of instructons removed would have had limited relevance in any case.
This compact set of memory-reference instructions is based on that used in compact mode, but with one important change. Since the full set of conditional jump, subroutine jump, and loop instructions is present elsewhere in this mode, it wasn't necessary to reserve space for a reduced subset of those instructions adjacent to the compact memory reference instructions in this mode.
Thus, an additional form of indexed instruction is provided with these characteristics:
The seven-bit opcodes are the same as those of the register-to-register instructions, but with the two most significant bits in the second halfword of the instruction.
The scratchpad registers are used as base registers for these instructions instead of the normal base registers.
These instructions use indirect addressing with post-indexing.
The eleven-bit address field in the instruction is shifted left two or three bits before use, depending on whether 32-bit or 64-bit addressing is in effect.
Thus, on the one hand, the compact memory-reference instructions allow the seven base registers from base register 1 through 7 to each point to an area of up to 65,536 bytes, which can contain simple variables.
On the other hand, instead of trying to fit all the arrays used by a program into these areas, which might mean that a whole base register is used up in order to allow a single huge array to be referenced, each of the seven scratchpad registers from scratchpad register 1 through 7 now points to a list of up to 2,048 addresses of arrays.
Thus, just as programs are free to use a large number of simple variables, they are also free to use a large number of arrays, restricted primarily by the amount of memory available, without the need to reload the base registers.
The cost of this feature, of course, is the extra memory access required due to resorting to indirect addressing. Because of this cost, the simple alternative of an indexed instruction where the index register is specified but the destination register must be register zero is also provided.
The opcodes of the memory-reference and register-to-register instructions in this format are:
Indexed Register Three-Address
------------- ------ ------
0406xx 0x0xxx 0000xx 060xxx 00xxxx SWB Swap Byte
0416xx 0x0xxx 0001xx 060xxx 01xxxx CB Compare Byte
0426xx 0x0xxx 0002xx 060xxx 02xxxx LB Load Byte
0436xx 0x0xxx STB Store Byte
0446xx 0x0xxx 0004xx 060xxx 04xxxx AB Add Byte
0456xx 0x0xxx 0005xx 060xxx 05xxxx SB Subtract Byte
0506xx 0x0xxx 0010xx 060xxx 10xxxx IB Insert Byte
0516xx 0x0xxx 0011xx 060xxx 11xxxx UCB Unsigned Compare Byte
0526xx 0x0xxx 0012xx 060xxx 12xxxx ULB Unsigned Load Byte
0536xx 0x0xxx 0013xx 060xxx 13xxxx XB XOR Byte
0546xx 0x0xxx 0014xx 060xxx 14xxxx NB AND Byte
0556xx 0x0xxx 0015xx 060xxx 15xxxx OB OR Byte
0576xx 0x0xxx 0017xx 060xxx 17xxxx STGB Store if Greater Byte
0407xx 0x0xxx 0020xx 061xxx 00xxxx SWH Swap Halfword
0417xx 0x0xxx 0021xx 061xxx 01xxxx CH Compare Halfword
0427xx 0x0xxx 0022xx 061xxx 02xxxx LH Load Halfword
0437xx 0x0xxx STH Store Halfword
0447xx 0x0xxx 0024xx 061xxx 04xxxx AH Add Halfword
0457xx 0x0xxx 0025xx 061xxx 05xxxx SH Subtract Halfword
0467xx 0x0xxx 0026xx 061xxx 06xxxx MH Multiply Halfword
0477xx 0x0xxx 0027xx 061xxx 07xxxx DH Divide Halfword
0507xx 0x0xxx 0030xx 061xxx 10xxxx IH Insert Halfword
0517xx 0x0xxx 0031xx 061xxx 11xxxx UCH Unsigned Compare Halfword
0527xx 0x0xxx 0032xx 061xxx 12xxxx ULH Unsigned Load Halfword
0537xx 0x0xxx 0033xx 061xxx 13xxxx XH XOR Halfword
0547xx 0x0xxx 0034xx 061xxx 14xxxx NH AND Halfword
0557xx 0x0xxx 0035xx 061xxx 15xxxx OH OR Halfword
0567xx 0x0xxx 0036xx 061xxx 16xxxx MEH Multiply Extensibly Halfword
0577xx 0x0xxx 0037xx 061xxx 17xxxx DEH Divide Extensibly Halfword
0406xx 0x1xxx 0040xx 062xxx 00xxxx SW Swap
0416xx 0x1xxx 0041xx 062xxx 01xxxx C Compare
0426xx 0x1xxx 0042xx 062xxx 02xxxx L Load
0436xx 0x1xxx ST Store
0446xx 0x1xxx 0044xx 062xxx 04xxxx A Add
0456xx 0x1xxx 0045xx 062xxx 05xxxx S Subtract
0466xx 0x1xxx 0046xx 062xxx 06xxxx M Multiply
0476xx 0x1xxx 0047xx 062xxx 07xxxx D Divide
0517xx 0x1xxx 0051xx 062xxx 11xxxx UC Unsigned Compare
0537xx 0x1xxx 0053xx 062xxx 13xxxx X XOR
0547xx 0x1xxx 0054xx 062xxx 14xxxx N AND
0557xx 0x1xxx 0055xx 062xxx 15xxxx O OR
0567xx 0x1xxx 0056xx 062xxx 16xxxx ME Multiply Extensibly
0577xx 0x1xxx 0057xx 062xxx 17xxxx DE Divide Extensibly
0406xx 0x1xxx 0060xx 063xxx 00xxxx SWL Swap Long
0416xx 0x1xxx 0061xx 063xxx 01xxxx CL Compare Long
0426xx 0x1xxx 0062xx 063xxx 02xxxx LL Load Long
0436xx 0x1xxx STL Store Long
0446xx 0x1xxx 0064xx 063xxx 04xxxx AL Add Long
0456xx 0x1xxx 0065xx 063xxx 05xxxx SL Subtract Long
0466xx 0x1xxx 0066xx 063xxx 06xxxx ML Multiply Long
0476xx 0x1xxx 0067xx 063xxx 07xxxx DL Divide Long
0517xx 0x1xxx 0071xx 063xxx 11xxxx UCL Unsigned Compare Long
0537xx 0x1xxx 0073xx 063xxx 13xxxx XL XOR Long
0547xx 0x1xxx 0074xx 063xxx 14xxxx NL AND Long
0557xx 0x1xxx 0075xx 063xxx 15xxxx OL OR Long
0567xx 0x1xxx 0076xx 063xxx 16xxxx MEL Multiply Extensibly Long
0577xx 0x1xxx 0077xx 063xxx 17xxxx DEL Divide Extensibly Long
0406xx 1x0xxx 0100xx 064xxx 00xxxx SWM Swap Medium
0416xx 1x0xxx 0101xx 064xxx 01xxxx CM Compare Medium
0426xx 1x0xxx 0102xx 064xxx 02xxxx LM Load Medium
0436xx 1x0xxx STM Store Medium
0446xx 1x0xxx 0104xx 064xxx 04xxxx AM Add Medium
0456xx 1x0xxx 0105xx 064xxx 05xxxx SM Subtract Medium
0466xx 1x0xxx 0106xx 064xxx 06xxxx MM Multiply Medium
0476xx 1x0xxx 0107xx 064xxx 07xxxx DM Divide Medium
0506xx 1x0xxx 0110xx 064xxx 10xxxx MEUM Multiply Extensibly Unnormalized Medium
0516xx 1x0xxx 0111xx 064xxx 11xxxx DEUM Divide Extensibly Unnormalized Medium
0526xx 1x0xxx 0112xx 064xxx 12xxxx LUM Load Unnormalized Medium
0536xx 1x0xxx 0113xx STUM Store Unnormalized Medium
0546xx 1x0xxx 0114xx 064xxx 14xxxx AUM Add Unnormalized Medium
0556xx 1x0xxx 0115xx 064xxx 15xxxx SUM Subtract Unnormalized Medium
0566xx 1x0xxx 0116xx 064xxx 16xxxx MUM Multiply Unnormalized Medium
0576xx 1x0xxx 0117xx 064xxx 17xxxx DUM Divide Unnormalized Medium
0407xx 1x0xxx 0120xx 065xxx 00xxxx SWF Swap Floating
0417xx 1x0xxx 0121xx 065xxx 01xxxx CF Compare Floating
0427xx 1x0xxx 0122xx 065xxx 02xxxx LF Load Floating
0437xx 1x0xxx STF Store Floating
0447xx 1x0xxx 0124xx 065xxx 04xxxx AF Add Floating
0457xx 1x0xxx 0125xx 065xxx 05xxxx SF Subtract Floating
0467xx 1x0xxx 0126xx 065xxx 06xxxx MF Multiply Floating
0477xx 1x0xxx 0127xx 065xxx 07xxxx DF Divide Floating
0507xx 1x0xxx 0130xx 065xxx 10xxxx MEU Multiply Extensibly Unnormalized
0517xx 1x0xxx 0131xx 065xxx 11xxxx DEU Divide Extensibly Unnormalized
0527xx 1x0xxx 0132xx 065xxx 12xxxx LU Load Unnormalized
0537xx 1x0xxx 0133xx STU Store Unnormalized
0547xx 1x0xxx 0134xx 065xxx 14xxxx AU Add Unnormalized
0557xx 1x0xxx 0135xx 065xxx 15xxxx SU Subtract Unnormalized
0567xx 1x0xxx 0136xx 065xxx 16xxxx MU Multiply Unnormalized
0577xx 1x0xxx 0137xx 065xxx 17xxxx DU Divide Unnormalized
0406xx 1x1xxx 0140xx 066xxx 00xxxx SWD Swap Double
0416xx 1x1xxx 0141xx 066xxx 01xxxx CD Compare Double
0426xx 1x1xxx 0142xx 066xxx 02xxxx LD Load Double
0436xx 1x1xxx STD Store Double
0446xx 1x1xxx 0144xx 066xxx 04xxxx AD Add Double
0456xx 1x1xxx 0145xx 066xxx 05xxxx SD Subtract Double
0466xx 1x1xxx 0146xx 066xxx 06xxxx MD Multiply Double
0476xx 1x1xxx 0147xx 066xxx 07xxxx DD Divide Double
0506xx 1x1xxx 0150xx 066xxx 10xxxx MEUD Multiply Extensibly Unnormalized Double
0516xx 1x1xxx 0151xx 066xxx 11xxxx DEUD Divide Extensibly Unnormalized Double
0526xx 1x1xxx 0152xx 066xxx 12xxxx LUD Load Unnormalized Double
0536xx 1x1xxx 0153xx STUD Store Unnormalized Double
0546xx 1x1xxx 0154xx 066xxx 14xxxx AUD Add Unnormalized Double
0556xx 1x1xxx 0155xx 066xxx 15xxxx SUD Subtract Unnormalized Double
0566xx 1x1xxx 0156xx 066xxx 16xxxx MUD Multiply Unnormalized Double
0576xx 1x1xxx 0157xx 066xxx 17xxxx DUD Divide Unnormalized Double
0407xx 1x1xxx 0160xx 067xxx 00xxxx SWQ Swap Quad
0417xx 1x1xxx 0161xx 067xxx 01xxxx CQ Compare Quad
0427xx 1x1xxx 0162xx 067xxx 02xxxx LQ Load Quad
0437xx 1x1xxx 0163xx STQ Store Quad
0447xx 1x1xxx 0164xx 067xxx 04xxxx AQ Add Quad
0457xx 1x1xxx 0165xx 067xxx 05xxxx SQ Subtract Quad
0467xx 1x1xxx 0166xx 067xxx 06xxxx MQ Multiply Quad
0477xx 1x1xxx 0167xx 067xxx 07xxxx DQ Divide Quad
0507xx 1x1xxx 0170xx 067xxx 10xxxx MEUQ Multiply Extensibly Unnormalized Quad
0517xx 1x1xxx 0171xx 067xxx 11xxxx DEUQ Divide Extensibly Unnormalized Quad
0527xx 1x1xxx 0172xx 067xxx 12xxxx LUQ Load Unnormalized Quad
0537xx 1x1xxx 0173xx STUQ Store Unnormalized Quad
0547xx 1x1xxx 0174xx 067xxx 14xxxx AUQ Add Unnormalized Quad
0557xx 1x1xxx 0175xx 067xxx 15xxxx SUQ Subtract Unnormalized Quad
0567xx 1x1xxx 0176xx 067xxx 16xxxx MUQ Multiply Unnormalized Quad
0577xx 1x1xxx 0177xx 067xxx 17xxxx DUQ Divide Unnormalized Quad
070xxx 00xxxx SWHG Swap High
070xxx 01xxxx CHG Compare High
070xxx 02xxxx LHG Load High
070xxx 03xxxx STHG Store High
070xxx 04xxxx AHG Add High
070xxx 05xxxx SHG Subtract High
070xxx 06xxxx MHG Multiply High
070xxx 07xxxx DHG Divide High
070xxx 11xxxx UCHG Unsigned Compare High
070xxx 13xxxx XHG XOR High
070xxx 14xxxx NHG AND High
070xxx 15xxxx OHG OR High
071xxx 00xxxx SFSWL Simple Floating Swap Halfword
071xxx 01xxxx SFCL Simple Floating Compare Halfword
071xxx 02xxxx SFLL Simple Floating Load Halfword
071xxx 04xxxx SFAL Simple Floating Add Halfword
071xxx 05xxxx SFSL Simple Floating Subtract Halfword
071xxx 06xxxx SFML Simple Floating Multiply Halfword
071xxx 07xxxx SFDL Simple Floating Divide Halfword
071xxx 10xxxx SFMEUH Simple Floating Multiply Extensibly Unnormalized Halfword
071xxx 11xxxx SFDEUH Simple Floating Divide Extensibly Unnormalized Halfword
071xxx 12xxxx SFLUH Simple Floating Load Unnormalized Halfword
071xxx 14xxxx SFAUH Simple Floating Add Unnormalized Halfword
071xxx 15xxxx SFSUH Simple Floating Subtract Unnormalized Halfword
071xxx 16xxxx SFMUH Simple Floating Multiply Unnormalized Halfword
071xxx 17xxxx SFDUH Simple Floating Divide Unnormalized Halfword
072xxx 00xxxx SFSW Simple Floating Swap
072xxx 01xxxx SFC Simple Floating Compare
072xxx 02xxxx SFL Simple Floating Load
072xxx 04xxxx SFA Simple Floating Add
072xxx 05xxxx SFS Simple Floating Subtract
072xxx 06xxxx SFM Simple Floating Multiply
072xxx 07xxxx SFD Simple Floating Divide
072xxx 00xxxx SFMEU Simple Floating Multiply Extensibly Unnormalized
072xxx 01xxxx SFDEU Simple Floating Divide Extensibly Unnormalized
072xxx 02xxxx SFLU Simple Floating Load Unnormalized
072xxx 04xxxx SFAU Simple Floating Add Unnormalized
072xxx 05xxxx SFSU Simple Floating Subtract Unnormalized
072xxx 06xxxx SFMU Simple Floating Multiply Unnormalized
072xxx 07xxxx SFDU Simple Floating Divide Unnormalized
073xxx 00xxxx SFSWL Simple Floating Swap Long
073xxx 01xxxx SFCL Simple Floating Compare Long
073xxx 02xxxx SFLL Simple Floating Load Long
073xxx 04xxxx SFAL Simple Floating Add Long
073xxx 05xxxx SFSL Simple Floating Subtract Long
073xxx 06xxxx SFML Simple Floating Multiply Long
073xxx 07xxxx SFDL Simple Floating Divide Long
073xxx 10xxxx SFMEUL Simple Floating Multiply Extensibly Unnormalized Long
073xxx 11xxxx SFDEUL Simple Floating Divide Extensibly Unnormalized Long
073xxx 12xxxx SFLUL Simple Floating Load Unnormalized Long
073xxx 14xxxx SFAUL Simple Floating Add Unnormalized Long
073xxx 15xxxx SFSUL Simple Floating Subtract Unnormalized Long
073xxx 16xxxx SFMUL Simple Floating Multiply Unnormalized Long
073xxx 17xxxx SFDUL Simple Floating Divide Unnormalized Long