[Next] [Up] [Previous]

The Simple Floating Type

Also with this prefix are a series of unusual floating-point arithmetic instructions which are performed using the integer arithmetic unit:

000400 120xxx  SFSWH  Simple Floating Swap Halfword
000400 121xxx  SFCH   Simple Floating Compare Halfword
000400 122xxx  SFLH   Simple Floating Load Halfword
000400 123xxx  SFSTH  Simple Floating Store Halfword
000400 124xxx  SFAH   Simple Floating Add Halfword
000400 125xxx  SFSH   Simple Floating Subtract Halfword
000400 126xxx  SFMH   Simple Floating Multiply Halfword
000400 127xxx  SFDH   Simple Floating Divide Halfword

000400 130xxx  SFMEUH Simple Floating Multiply Extensibly Unnormalized Halfword
000400 131xxx  SFDEUH Simple Floating Divide Extensibly Unnormalized Halfword
000400 132xxx  SFLUH  Simple Floating Load Unnormalized Halfword
000400 133xxx  SFSTUH Simple Floating Store Unnormalized Halfword
000400 134xxx  SFAUH  Simple Floating Add Unnormalized Halfword
000400 135xxx  SFSUH  Simple Floating Subtract Unnormalized Halfword
000400 136xxx  SFMUH  Simple Floating Multiply Unnormalized Halfword
000400 137xxx  SFDUH  Simple Floating Divide Unnormalized Halfword

000500 100xxx  SFSW   Simple Floating Swap
000500 101xxx  SFC    Simple Floating Compare
000500 102xxx  SFL    Simple Floating Load
000500 103xxx  SFST   Simple Floating Store
000500 104xxx  SFA    Simple Floating Add
000500 105xxx  SFS    Simple Floating Subtract
000500 106xxx  SFM    Simple Floating Multiply
000500 107xxx  SFD    Simple Floating Divide

000500 110xxx  SFMEU  Simple Floating Multiply Extensibly Unnormalized
000500 111xxx  SFDEU  Simple Floating Divide Extensibly Unnormalized
000500 112xxx  SFLU   Simple Floating Load Unnormalized
000500 113xxx  SFSTU  Simple Floating Store Unnormalized
000500 114xxx  SFAU   Simple Floating Add Unnormalized
000500 115xxx  SFSU   Simple Floating Subtract Unnormalized
000500 116xxx  SFMU   Simple Floating Multiply Unnormalized
000500 117xxx  SFDU   Simple Floating Divide Unnormalized

000500 120xxx  SFSWL  Simple Floating Swap Long
000500 121xxx  SFCL   Simple Floating Compare Long
000500 122xxx  SFLL   Simple Floating Load Long
000500 123xxx  SFSTL  Simple Floating Store Long
000500 124xxx  SFAL   Simple Floating Add Long
000500 125xxx  SFSL   Simple Floating Subtract Long
000500 126xxx  SFML   Simple Floating Multiply Long
000500 127xxx  SFDL   Simple Floating Divide Long

000500 130xxx  SFMEUL Simple Floating Multiply Extensibly Unnormalized Long
000500 131xxx  SFDEUL Simple Floating Divide Extensibly Unnormalized Long
000500 132xxx  SFLUL  Simple Floating Load Unnormalized Long
000500 133xxx  SFSTUL Simple Floating Store Unnormalized Long
000500 134xxx  SFAUL  Simple Floating Add Unnormalized Long
000500 135xxx  SFSUL  Simple Floating Subtract Unnormalized Long
000500 136xxx  SFMUL  Simple Floating Multiply Unnormalized Long
000500 137xxx  SFDUL  Simple Floating Divide Unnormalized Long

These instructions involve pairs of registers, and operands twice the length of their associated integer type. They work on floating-point numbers represented as pairs of integers.

The first integer is the mantissa, which is a signed two's complement number, and the second integer is the exponent, which is also a signed two's complement number.

In the case of the simple floating long type, since a pair of arithmetic/index registers are required for a 64-bit value, the instructions work on groups of four registers. (Only a pair of registers is required in the case of the 64-bit supplementary arithmetic/index registers; but in that case, due to the arithmetic operations required, a pair of registers is still used in the case of operands of the shorter types as well.)

This allows the computer to match the capabilities of some early computers which used this basic method of achieving the ability to do floating-point arithmetic without adding extensive new logic for performing such arithmetic, most notably the Recomp II.

In addition, versions of the conversion instructions for this floating-point mode are provided here as well, which have this form:

and these opcodes:

000400 1010xx 00xxxx     CVPSFH    Convert Packed to Simple Floating Halfword
000400 1014xx 00xxxx     CVSFHP    Convert Simple Floating Halfword to Packed
000400 1020xx 00xxxx     CVPSF     Convert Packed to Simple Floating
000400 1024xx 00xxxx     CVSFP     Convert Simple Floating to Packed
000400 1030xx 00xxxx     CVPSFL    Convert Packed to Simple Floating Long
000400 1034xx 00xxxx     CVSFLP    Convert Simple Floating Long to Packed

These instructions have the same format as the conversions between packed decimal and floating-point types, consisting of the prefix 000400 preceding the type conversion for the integer type which constitutes the components of the simple floating type in question.

Note that, due to the large magnitudes possible with this floating-point format, execution times for these instructions may be longer than for the corresponding conversions to and from conventional floating-point types.

Simple floating operands in registers always begin with an even-numbered register: where the operand is of long type, since each of the elements occupies a pair of registers, only arithmetic/index registers 0 and 4 can be used as the source or destination of a long simple floating operation.

These operations, unlike the register packed operations, can be performed using the long vector arithmetic unit as well. This is particularly useful with the simple floating instructions (for which only long operations require the use of an even numbered register, since the supplementary arithmetic/index registers are 64 bits long, not 32 bits long) when the common floating-point format is selected, as it can increase by half the amount of floating-point operations that can be concurrent at a given instant.

This may not lead to the full expected corresponding speed increase, however, since some implementations may apply optimizations to the floating-point arithmetic units that are not applied to the integer arithmetic units. Also, for the long simple floating instructions, since it is envisaged little extra hardware will be added for this relatively little-used function, multiplications will require two steps rather than one, to make use of circuits designed only to multiply numbers of half the width of the complete number; this will be no problem for the ordinary simple floating-point format, but it will affect simple floating-point instructions when the format is modified to be the common floating-point format.

Instructions in the vector register mode that would normally handle up to 64 operands instead would handle up to 32 operands of the simple floating type, and are coded as if each simple floating operand is simply two successive integer operands. However, the start of a range must be even, the end of a range must be odd, and mask bits must be on or off in pairs, so that any simple floating value composed of two integers has both its parts either included or excluded from a given simple floating vector operation, or the results will be undefined.

Although it may appear that the simple floating halfword type is of limited utility, since a signed 16-bit number provides about four and a half decimal digits of precision, this type can be useful under some circumstances:

Because arithmetic on operands of the Simple Floating type is performed using the hardware primarily intended for integer arithmetic, not only are no guard bits retained in registers between operations on values of this type, but no guard bit or sticky bit is used with a value of this type during an operation. Therefore, the results even of simple operations on values of the Simple Floating type are not guaranteed to be the closest approximation to the correct result expressible in the format.

Only the Simple Floating type has the latter limitation, although the former limitation, of no guard bits retained between operations, is shared by some other floating-point types. The following table summarizes the situation.

Floating-point Type Guard, Round, and Sticky Bits Additional Guard Bits
Floating-Point Shorter than 128 bits in Regular Floating-Point Registers Yes Yes
128-bit Floating-Point Yes No
Floating-Point in Short Vector Registers Yes No
Simple Floating Type No No

[Next] [Up] [Previous]