This section deals with a group of instructions created by the instruction prefix code. The instructions dealt with in this section are available in Compact Mode (and also the equivalent Local Mode) as well as Normal Mode (and also the equivalent Scratchpad Mode and Condensed Mode). They are also available in Simple Mode, but with different opcodes.
As we saw at the beginning of this section, a 16-bit instruction halfword of the form
usually indicates a long instruction, with the three bits repeated twice in the fields labelled abc indicating the number of additional 16-bit halfwords at the end of the instruction, and the p bit, if present, indicating that between the first 16 bits and those additional 16-bit halfwords, an indeterminate number of halfwords are present in the instruction, indicated by all but the last of them beginning with a 1, and the last beginning with a 0.
There are two exceptions to this scheme; these use codes that would have reduntantly indicated instructions 16 bits and 32 bits in length.
An instruction halfword of the form:
is used to begin the long vector instructions and related instructions, which are two-address and three-address instructions where for each of the two or three possible operands, the need for additional instruction words is indicated independently, in a structure reminiscent of the basic instructions of the historic PDP-11 minicomputer from the Digital Equipment Corporation.
In Simple Mode, long vector instructions instead begin with instruction halfwords of the form:
An instruction halfword of the form:
is used as a 16-bit prefix to an instruction, extending opcode space, after which a normal instruction follows. While the decoding of the instruction to determine its function may differ from that of an unprefixed instruction, its length will be determined in exactly the same way as an unprefixed instruction. (In Compact Mode, this prefix is also valid, but what follows the prefix is decoded using the length rules that applied in Normal Mode, not the modified ones that apply to instructions in Compact Mode.) Note that multiple consecutive prefixes are possible.
In Simple Mode, this prefix instead takes the form:
Instead of indicating a long instruction in which this 16-bit word is followed by zero or more 16-bit words starting with 1 and then one 16-bit word starting with 0, it indicates a prefix of that form.
When the six-bit code in a prefix is of the form 0xxxxx this code is largely treated as a supplement to the opcode of the instruction following, to enable operations on special data types, although some changes to instruction decoding (not involving length) also take place. Two prefixes of this type indicate different special data types for the two operands of an instruction: this is used to indicate conversion instructions that convert between compressed decimal and simple floating formats.
Also, what would be a 32-bit instruction of the form 141xx0 yyyyyy is instead used as a 32-bit prefix to an instruction. Where the xx field contains a value from 00 to 37, octal, that is considered to indicate the same supplemental opcode bits as those six bits beginning with a zero would indicate in a 16-bit prefix, and the second halfword of the prefix is used for supplemental information. This format is used for the targeted arithmetic instructions for decimal exponent floating-point and floating register compressed decimal arithmetic.
Where the first bit of the xx field is a 1, on the other hand, the prefix may be completely unrelated to any 16-bit prefix.
This illustration shows the form of most of the instructions with which we will be dealing in this section:
One exception is the compressed decimal instructions, for which the same prefix is applied, but to the packed decimal instructions, as the compressed decimal instructions are memory-to-memory instructions similar to packed decimal instructions.
Another exception is the type conversion instructions used with the Simple Floating type.
Those memory-reference instructions which were shortened to 16 bits in length to create the branch and floating single-operand instructions by having a base register value of zero normally are now used, in combination with the prefix, to create memory-reference instructions which are shortened to their corresponding register-to-register forms when they have a base register value of zero, and which have an effective 10-bit opcode, split between the first two 16-bit halfwords of the instruction.
Note that these instructions may address unaligned operands.
When the first three bits of the opcode are zero, the remaining seven bits are interpreted as in the normal 16-bit register-to-register instructions, allowing alternate versions of the memory-reference instructions which can act on unaligned source operands.
Having a longer opcode, these instructions may manipulate operands of additional data types, beyond those which can be manipulated by the normal memory-reference instructions.
These types are:
Also, some additional operations on the regular data types are provided using these instruction formats.
An additional group of instructions of this nature facilitates working with unnormalized numbers that encode significance:
002000 102xxx LUAIM Load Unnormalized as Interval Medium 002000 103xxx SIAUM Store Interval as Unnormalized Medium 002000 106xxx LUAIMDE Load Unnormalized as Interval Medium Decimal Exponent 002000 107xxx SIAUMDE Store Interval as Unnormalized Medium Decimal Exponent 002000 112xxx LUAI Load Unnormalized as Interval 002000 113xxx SIAU Store Interval as Unnormalized 002000 114xxx SFLUAIH Simple Floating Load Unnormalized as Interval Halfword 002000 115xxx SFSIAUH Simple Floating Store Interval as Unnormalized Halfword 002000 122xxx LUAID Load Unnormalized as Interval Double 002000 123xxx SIAUD Store Interval as Unnormalized Double 002000 124xxx SFLUAI Simple Floating Load Unnormalized as Interval 002000 125xxx SFSIAU Simple Floating Store Interval as Unnormalized 002000 126xxx LUAIDDE Load Unnormalized as Interval Double Decimal Exponent 002000 127xxx SIAUDDE Store Interval as Unnormalized Double Decimal Exponent 002000 132xxx LUAIQ Load Unnormalized as Interval Quad 002000 133xxx SIAUQ Store Interval as Unnormalized Quad 002000 134xxx SFLUAIL Simple Floating Load Unnormalized as Interval Long 002000 135xxx SFSIAUL Simple Floating Store Interval as Unnormalized Long
These instructions convert between an unnormalized number, which may be in a register or in storage, and a pair of numbers in consecutive registers the first of which is an even-numbered register. The LUAI instructions load the first register with the unnormalized number normalized by padding it with zeroes, and the second register with the unnormalized number normalized and padded on the right with ones. The SIAU instructions attempt to find the unnormalized number which most tightly includes the two numbers in the two registers that are the destination operand of the instruction to store in the source operand. If the two components of the destination operand being converted and stored have the same sign, the one that has the lowest magnitude (the lowest absolute value) must be in the lower numbered register.