When the data memory width is set for a 32-bit word, normally Medium floating point numbers occupy 48 bits of storage, but they occupy 80 bits for the temporary real value if compatibility with the IEEE-478 floating-point standard is chosen. In both cases, such numbers are built up out of an odd number of 16-bit halfwords in storage. This provides compatibility with other types of variable, because they are built up from a standard unit. However, as they are longer than 16 bits in length, but aligned on 16-bit boundaries, fetching a fully aligned Medium floating-point number from memory may result in a need for two memory accesses, regardless of the width of the path to memory, the same way retrieving an unaligned operand would.
An alternative mode of operation is provided which avoids this. In this mode, instead of a Medium floating-point number being built up of an odd number of smaller units, it is an odd fraction of a larger unit. In some cases, this will result in a small number of bits being left over.
This, in the normaal mode with a 32 bit word, if Subdivided Medium operation is selected, the Medium floating point type will be either 51 bits long, five such numbers being stored in each 256 bits of memory with one bit left over, or 85 bits long, three such numbers being stored in each 256 bits of memory with one bit left over.
The intent of this is to avoid, for a data bus width that is a sufficiently high power of two multiple of the basic word length, ever being required to read memory more than once to fetch an operand of the Medium floating-point type.
Thus, if the data path to memory is 256 bits wide, it makes sense to use 51-bit medium floating-point numbers, but otherwise not using subdivided medium floating-point, and staying with 48-bit medium floating-point numbers, makes more sense, since while 51-bit numbers do not cross 256-bit boundaries, they will cross 128-bit boundaries and 64-bit boundaries just as often, or more so, than 48-bit mediums.
The first of a group of subdivided medium floating-point numbers can be referenced by its actual address. In the case where memory is addressed normally as 8-bit bytes, a 256-bit unit of memory is divided either into three pieces, each 85 bits long, or five pieces, each 53 bits long. These do not have normal addresses. Since the Medium floating-point type is normally halfword-aligned, it would be appropriate to use such addresses in this case to indicate which of the floating-point numbers of irregular length within a 256-bit block is desired.
So that the address of a floating-point number actually points to a location that is part of the floating-point number, a 256-bit block containing five 53-bit floating-point numbers followed by one unused bit will have the numbers within it addressed as if the first one begins at the beginning of the block, and each one is 48 bits long, and there are two unused bytes following the first number.
In the other cases, the addressing works as follows:
Halfword size in bits: 16 12 18 20 30
Subdivided Medium (standard) 85 -- -- -- 80
256/3 240/3
addressing length: 64 60
Subdivided Medium (compatible) -- 64 48 -- 48
192/3 144/3 240/5
addressing length: 48 36 30
Subdivided Medium (all others) 51 64 48 53 48
256/5 192/3 144/3 160/3 240/5
32 48 36 40 30
In each case, the first number in a block is addressed as though it is at the beginning of the block, and remaining numbers are addressed as if they are numbers of the addressing length, right-aligned against the end of the block, which may be 256 bits long in 32-bit word mode, 192 bits long in 24-bit word mode, 144 bits long in 36-bit word mode, 160 bits long in 40-bit word mode, or 240 bits long in 60-bit word mode.
Alternate sizes are available for single-precision and double-precision floating-point as well. While this does not cure any alignment problem, it also does not cause one. 36 bits, rather than 32 bits, is considered the preferred length for a single-precision floating-point number, and 60 bits is considered adequate for a double-precision floating-point number. Hence, it is potentially appropriate to consider an alternate length for floating-pont numbers.
For subdivided floating:
Halfword size in bits: 16 12 18 20 30
Subdivided Floating (standard) 36 38 -- -- 34
256/7 192/5 240/7
addressing length: 32 48 30
Subdivided Floating (compatible) 36 -- -- -- --
256/7
addressing length: 32
Subdivided Floating (all others) 36 38 -- -- 34
256/7 192/5 240/7
32 48 30
and for subdivided double:
Halfword size in bits: 16 12 18 20 30
Subdivided Double (standard) 85 64 57 -- --
256/3 192/3 288/5
addressing length: 64 48 36
Subdivided Double (compatible) -- 64 -- -- --
192/3
addressing length: 48
Subdivided Double (all others) 64 57 64 --
-- 192/3 288/5 320/5
48 36 40
Note that in the tables above, the memory word, whether 256, 192, 288, 320, or 240 bits in width, is divided into either 3, 5, or 7 parts (and, in a few cases, by 2 as well).
Division, even by simple fixed quantities such as 3, 5, or 7 (as opposed to a power of two), cannot be performed at speeds appropriate to address calculation.
As noted above, the normal mode of addressing numbers stored with this technique is to treat the memory word as divided into 4 or 8 parts, the last few of which are unused. Array addressing is left to software.
When multiplicative block addressing is enabled, the value in the index register continues to behave as a pure number, but now it specifies a displacement in units of the length of the floating-point numbers addressed, instead of in bytes.
This is achieved as follows:
In the case where division by 3 would seem to be required, instead, the part of the index register before the last 5 bits is multiplied by 11. That way, it points to a block of 11 memory words, which contain 33 floating-point numbers of the desired type. The last five bits in the index register are used to select one of 32 such numbers, the 33rd being left unused.
When division by 5 is indicated, the last 6 bits are set aside, and the first part is multiplied by 13, so that it points to a block of 65 numbers of which 64 are used.
When division by 7 is indicated, the last 8 bits are set aside, and the first part is multiplied by 37, so that it points to a block of 259 numbers of which 256 are used.
In the cases above where 144 is used as a memory unit instead of 288, or 160 instead of 320, one additional bit is set aside at the end, and the blocks are of the larger memory unit, so that the parts skipped are consistent for different related types.
The basic principle of this technique is discussed here.
It is recommended that when multiplicative indexing is in use, base registers pointing to regions containing floating-point numbers of the applicable precision should contain addresses aligned on memory word boundaries; 256-bit boundaries when the normal data memory width is in effect.
Displacements must be aligned floating-point addresses, in terms of the addressing length given above; thus, for 36-bit and 51-bit floating-point numbers in a 256-bit memory word, they must be aligned on 32-bit boundaries.
The case where the basic address points to a data item other than the first in a memory word, and indexing is present, is defined for this architecture, and the definition is as follows: the basic address is split into two parts, the memory address of a memory word, and the number of a data item within that word.
If the instruction is not indexed, the number of the data item within the memory word must be a valid one; for example, for 51-bit floats in a 256-bit memory word, the values 0, 1, 2, 3, and 4 are allowed; the values 5, 6, and 7 indicating an item having the addressing length of 32 bits are illegal, and may produce an error or unpredictable results.
In the case of an indexed address, the number of the data item is added to the index register contents before they are processed, and then the addresses of the memory word from the basic address and the displacement in memory words from the index register contents are added. In that case, the number of the data item may have any value for the bits it occupies, as the sum of that and the index register contents will undergo processing that allows for a data item in a different memory word than that indicated by the unindexed address to be referenced.