The 17-bit instructions
are made available when a block starts with `1111`

; the
last sixteen bits of the instruction appear in their normal position in the
instruction stream, the first bit appears within the block header.

The instructions to be described in this section have the formats shown in this diagram:

The diagram shows the different 17-bit instructions.

The 17-bit instructions do not include memory-reference instructions, or the subroutine jump instruction. However, while the set of 17-bit instructions is therefore not complete in itself, it is sufficient that a large proportion of the instructions in a program could be 17-bit instructions.

Line 1 gives the format of the operate instructions. Integer instructions reference the integer registers, and floating-point instructions reference the floating-point registers, as might be expected.

There are 96 possible opcodes, as the first two bits of an opcode may not be both 1, as these combinations are reserved for other 17-bit instructions.

The opcodes (with the first four bits appearing along the top of the chart, and the last three bits appearing on the right) are:

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 SWB IB SWH IH SW I SWL SWM SWF SWD SWQ 000 CB CH C CL CM CF CD CQ 001 LB ULB LH ULH L UL LL LM LF LD LQ 010 STB XB STH XH ST X STL XL STM STF STD STQ 011 AB NB AH NH A N AL NL AM AF AD AQ 100 SB OB SH OH S O SL OL SM SF SD SQ 101 MH MEH M ME ML MEL MM MF MD MQ 110 DH DEH D DE DL DEL DM DF DD DQ 111

The different instructions are:

For integer types:

M MULTIPLY Multiply the contents of the source and destination locations, placing the least significant part of the result of the same length as the two input operands in the destination location, with sign extension if that is shorter than the length of the destination register D DIVIDE Divide the contents of the source location by the contents of the destination location, placing the quotient in the destination location L LOAD Place the contents of the source operand in the destination register; if the type involved is smaller than the register, perform sign extension ST STORE Fill the destination location from the least significant part of the source location A ADD Add the contents of the source and destination locations, placing the result in the destination location S SUBTRACT Subtract the contents of the source location from those of the destination location, placing the result in the source location SW SWAP Exchange the contents of the source and destination locations C COMPARE Subtract the contents of the source location from the contents of the destination location, but with the operation modified so that overflow cannot possibly result, and set the condition codes appropriately without modifying the destination location I INSERT Fill the least significant bits of the destination register with the contents of the source location, leaving the rest of the destination register unaffected UL UNSIGNED LOAD Fill the least significant bits of the destination register with the contents of the source location, and clear the remaining more significant bits of the destination register X EXCLUSIVE OR Perform a bitwise Exclusive OR operation between the contents of the source and destination locations, placing the result in the desination location N AND Perform a bitwise Logical AND operation between the contents of the source and destination locations, placing the result in the desination location O OR Perform a bitwise Logical OR operation between the contents of the source and destination locations, placing the result in the desination location ME MULTIPLY EXTENSIBLY Multiply the contents of the source and destination locations. Take the full product, as an integer having twice the size as that of the source and the destination, and: - in the case of the halfword and integer versions of the instruction, place it in the destination register, with sign extension in the halfword version; - in the case of the long version of the instruction, place the most significannt half of the result in the destination register, which must be an even-numbered register, and place the least significant half of the result in the register following DE DIVIDE EXTENSIBLY Divide a destination operand of twice the length of that indicated by the instruction type (and located as the result of the MULTIPLY EXTENSIBLY instruction) by the source operand; store the double length quotient in the destination location (again following the MULTIPLY EXTENSIBLY result placement) and the single length remainder in the next register following those that are used. Whenever a result is not wide enough to fill a register, sign extension is performed. Division is performed giving a result as if both operands were converted to positive numbers before starting, with the signs then set afterwards to give a correct result based on the actual signs of the operands. Thus both the quotient and the remainder will be positive or zero if the dividend and divisor have the same sign, and both will be negative or zero if they are of opposite signs.

The possible integer types, and the suffixes that indicate them, are:

B BYTE An 8-bit two's complement integer H HALFWORD A 16-bit two's complement integer INTEGER A 32-bit two's complement integer L LONG A 64-bit two's complement integer

The integer registers are 64 bits long, to contain the longest of these types.

The available floating-point operations are SWAP, LOAD, STORE, ADD, SUBTRACT, MULTIPLY, and DIVIDE. Their functions are basically the same as those of the corresponding integer operations, except that floating-point arithmetic is performed.

The possible floating-point types for 16-bit instructions, and the suffixes that indicate them, are:

M MEDIUM A 48-bit floating-point number (preferably aligned on 16-bit boundaries) F FLOATING A 32-bit floating-point number D DOUBLE A 64-bit floating-point number Q QUAD A 128-bit floating-point number

with their formats as indicated within this diagram:

Support for the 80-bit type, corresponding to the temporary real format used with the Intel 8087 math coprocessor, has been droppoed, because its exponent size is incompatible with the newly defined IEEE 754 standard for a 128-bit floating type and, in addition, a 256-bit floating type.

Originally, it had been planned to have the 128-bit type of this architecture to be similar to 80-bit temporary real, but with a longer mantissa. Instead, it is now the standard type which also has a hidden first bit; it is the 512-bit type which now is generally similar in aspect to temporary real, but it has an exponent field that is five bits larger than that of the 80-bit type. The reason for this is to allow support, with an internal form that is 130 bits in length, of the 128-bit floating-point type defined in the latest versions of the IEEE 754 standard; having subsequently learned that it also defines a 256-bit floating-point type with a hidden first bit, the internal exponent field has been lengthened again so that it may be supported as well.

As a consequence of this, 128-bit floating-point numbers may be stored in even-numbered floating-point registers, but not in all the odd-numbered floating-point registers, as, since they have a hidden first bit in the mantissa, they must be converted to an internal form in the registers for efficient use in arithmetic. Their internal form, which is 130 bits long, has its first 128 bits in the form of the 128-bit floating-point numbers shown above, with the final two bits of the significand being placed in the first two bits (not the first two bits of the significand portion) of the following floating-point register.

Since so little of the second register is used, another scheme is also used to allow
floating-point numbers of this type to be stored in half of the *odd-numbered*
floating-point registers. Here, the last (rightmost) 84 bits of both the register
specified, and of the register two positions later, are allocated to the internal form
of such numbers.

The register specified contains the first 84 bits of the 128-bit floating-point form shown above; the register two positions later contains, in the leftmost portion of its last 84 bits, the remaining 46 significand bits required.

This scheme is also used for the internal form of 128-bit Decimal Floating Point numbers, which is also considerably shorter than 256 bits, but comes closer to the 160 bits which this scheme makes available.

As for the storage of 256-bit floating-point numbers in registers, while they will be able to be stored in pairs of consecutive floating-point registers where the number of the first register is a multiple of four, it appears that supporting them will require some additional circuitry over and above that required for 128-bit Decimal Floating Point numbers; an analogous scheme, but involving register pairs instead of registers, would allow 256-bit floating-point numbers to be stored not only in registers with numbers of the form 4n, but also in registers with numbers of the form 8n+2.

These instructions are then also suffixed RC for Register Compact to indicate the addressing mode.

Lines 2 through 5 of the diagram illustrate the shift and rotate short instructions. These are:

300xxx LSLLC Logical Shift Left Long Compact 304xxx LSRLC Logical Shift Right Long Compact 310xxx RLLC Rotate Left Long Compact 314xxx ASRLC Arithmetic Shift Right Long Compact 320xxx LSLC Logical Shift Left Compact 324xxx LSRC Logical Shift Right Compact 330xxx RLC Rotate Left Compact 334xxx ASRC Arithmetic Shift Right Compact 322xxx LSLHC Logical Shift Left Halfword Compact 326xxx LSRHC Logical Shift Right Halfword Compact 332xxx RLHC Rotate Left Halfword Compact 336xxx ASRHC Arithmetic Shift Right Halfword Compact 3230xx LSLBC Logical Shift Left Byte Compact 3270xx LSRBC Logical Shift Right Byte Compact 3330xx RLBC Rotate Left Byte Compact 3370xx ASRBC Arithmetic Shift Right Byte Compact

Logical right and left shifts insert zeroes; the arithmetic right shift inserts a copy of the existing value of the most significant bit into the leftmost position of the word so as to maintain the sign as either negative or non-negative.

An arithmetic left shift inserts zeroes into the leftmost end of a number regardless of its sign, just like a logical left shift, but it differs in that the overflow bit is set if a left shift results in a change of the sign of the value being shifted, instead of merely a carry out of that value; this difference is, however, not applicable to short instructions, as they may not alter the condition codes, not having space for a C bit.

In the 16-bit short instructions, there is no available separate region of opcode space for the rotate instructions, and so instead the arithmetic left shift is replaced by rotate left.

Line 6 of the diagram shows the branch instructions.

The displacement is an 8-bit signed value, in two's complement form, which may vary from
-128 to +127. The displacement is in units of 16 bits. No attempt is made to skip over values
corresponding to the 32-bit instruction slots containing header information in counting; the
displacement is an actual displacement in terms of the memory address, not a count of skipped
instructions. A displacement of zero refers to the position immediately following the
instruction. The target of a branch instruction *must* always be an actual executable
instruction, and not a setup directive, an immediate value, or any part of a 48-bit or 80-bit
instruction other than its first 16 bits.

The available branch instructions are:

3404xx BL Branch if Low 3410xx BE Branch if Equal 3414xx BLE Branch if Low or Equal 3420xx BH Branch if High 3424xx BNE Branch if Not Equal 3430xx BHE Branch if High or Equal 3434xx BNV Branch if No Overflow 3440xx BV Branch if Overflow 3450xx BC Branch if Carry 3454xx BNC Branch if No Carry 3474xx B Branch

Line 7 of the diagram of 17-bit short instructions, and the correspoonding line in the diagram of 15-bit short instructions, shows how condition values that are invalid result instead in an additional category of instructions which affect the flags used for predicated instructions.

3400xx CTF Condition to Flag Set flag to 1 if condition valid; set flag to 0 if condition not met 3460xx SFC Set Flag on Condition Set flag to 1 if condition met; leave it unaffected otherwise 3464xx CFC Clear Flag on Condition Set flag to 0 if condition met; leave it unaffected otherwise

Line 8 of the diagram of 17-bit short instructions, and the correspoonding line in the diagram of 15-bit short instructions, shows how an additional invalid condition value provides another special instruction:

3470xx SVC Supervisor Call

This instruction performs the equivalent of an interrupt from within software, allowing portions of the operating system not running in supervisor state to request services from the kernel, as well as possibly also allowing user programs to request services from the operating system.

One header type allows for 19-bit instructions, which permit a memory-reference instruction to share a 32-bit instruction slot with one of the 17-bit instructions described above, or even another 19-bit memory-reference instruction, with the aid of a few additional prefix bits.

The form of these instructions is shown below:

The X bit indicates indexing, using integer register 1 as the index register.

The ssB field, as with other memory-reference instructions, refers to one of registers 17 through 23 if nonzero, to be used as the base register.

The interpretation of the opcode field depends on the value of the T bit in the block header that provides for four-bit prefixes, and is as follows:

T=0 T=1 000 LH L 001 STH ST 010 L LL 011 ST STL 100 LF LF 101 STF STF 110 LD LD 111 STD STD

Since there's no room, even with 19 bits available, for a destination register field, the register operand will just have to always be register zero for these memory-to-register load and store instructions.