The formats of the basic 32-bit instructions for this architecture are shown in the two diagrams below:
First, the instructions that are 32 bits in length which can never affect the condition code bits, as they perform functions such as load and store, or jump, are shown.
The 32-bit form of basic load and store instructions is shown in lines 1 through 5.
For a memory-reference instruction, the five-bit destination register field specifies one of 32 registers, either the general-purpose registers for integer instructions, or the floating-point registers for floating-point instructions.
The index register field contains a number from 0 to 7, if it contains 0, the instruction is not indexed; if it contains any other value, that value indicates which general register is to be used as the index register for that instruction.
Lines 1 through five show the five possible formats for 32-bit memory-reference instructions.
In line 1, a three-bit field indicates the base register. It may contain any value from 1 to 7, which indicates that a general register from 25 to 31 respectively is used as the base register.
Line 2 of the original diagram shows the second possibility: a 15-bit displacement is included in the instruction, and general register 16 contains the starting point of the 32,768-byte area of memory to which the values of this displacement may refer.
Line 3 of the original diagram shows the third possibility. Here, the displacement is 12 bits long, and there is a three-bit ssB field (short source base) adjacent to it.
If that field contains a number from 1 to 7, it indicates that a register from 17 to 23, respectively, is used as a base register, the contents of which point to a 4,096-byte area in memory.
If that field contains a 0, then one of the possibilities shown in lines 4 and 5 of the diagram apply.
Line 4 of the original diagram shows this possibility: if the ssB field, containing a 0, is followed by a 0, then program-relative addressing is indicated.
The instruction now contains an 11-bit displacement, which is in units of bytes, but now it is a signed two's complement value from -1,024 to 1,023, relative to the position immediately after the end of the instruction. One particularly important application of this addressing mode is at the beginning of a main program or a subroutine, where a Jump to Subroutine instruction having the following instruction as its destination can be used to initialize a base register by means of which adresses referring to the program code can be constructed.
Line 5 of the original diagram shows the format for two other addressing modes.
If the ssB field,
containing a 0, is followed by 100, then it indicates Array Mode addressing.
Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit pointer to an array.
If indexing is present in the instruction, the contents of the selected register are added to that pointer in order to address an element of that array. Thus, Array Mode provides post-indexed indirect addressing in order to conveniently allow a program to refer to up to 512 arrays which are larger than 65,536 bytes in size without having to reload base registers in order to access them.
If the ssB field,
containing a 0, is followed by 101, then Address Table addressing is indicated.
Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit constant containing the effective address of the instruction.
If indexing is present in the instruction, the contents of the selected register are added to the initial effective address formed by adding the contents of register 17 to the displacement, so as to change which 64-bit constant is taken as the effective address.
Thus, Array Mode addressing provides pre-indexed indirection, and Address Table addressing provides post-indexed indirection. Array Mode addressing is useful for accesing data in multiple large arrays without reloading base registers, and Address Table addressing is useful for such things as multi-way jump tables.
If the ssB field, containing a 0, is followed by 110, then Array Mode with
Auto-Increment addressing is indicated. The displacement is in units of 64 bits, and
the contents of base register 17 are added
to the displacement after scaling to find the address to be used; this address may be indexed to form
the effective address, and, in addition, after the memory location at the effective address so calculated
is accessed, the index register is then incremented by the size of the operands of the instruction;
incremented by one if the instruction acts on bytes, having eight added to it if the instruction acts
on double-precision floating-point numbers, and so on. This includes adding six in the case of medium
floating-point numbers.
If the ssB field, containing a 0, is followed by 111, then Array Mode with
Flexible Auto-Increment
addressing is indicated. Here, if the instruction is indexed, the index register must be one of
registers 2, 4, or 6, and the amount by which it is incremented after memory access is found in the
following register.
Note that the bit combination corresponding to the illegal use of an odd-numbered index register with a memory-reference instruction in this mode is used for a header of the first type, as also shown, as it also serves as an instruction, in line 7.
The subroutine jump instruction makes use of the opcode which would indicate an "unsigned load long" instruction; since the long data type is as long as a complete integer register, such an operation is not needed; similarly, the opcode for "insert long" is used for Load Address instead.
The format of the subroutine jump is shown in line 6; the contents of the offset field, shifted one place to the left, are added to the address of the location immediately following the subroutine jump instruction to form the return address.
This allows more efficient and rapid processing of returns from subroutines when the subroutine jump instruction precedes space reserved for pseudo-immeidates and/or a block header, which stand between it and the next instruction to be executed.
Lines 7 and 8 of the diagram show the formats of the multiple-register load and store instructions:
300xxxxxxxx LM Load Multiple 304xxxxxxxx STM Store Multiple 310xxxxxxxx LMF Load Multiple Floating 314xxxxxxxx STMF Store Multiple Floating
Note that these instructions, in particular the ones for the floating-point registers, load and store their contents in raw internal form. Because of the complexities of the IEEE 754 format for floating-point numbers, they are converted to an internal form when loaded into the floating-point registers, and converted back to the standard form when stored from those registers, to allow register-to-register arithmetic to proceed more quickly.
The Long Vector load/store instructions in lines 11 and 12 provide a limited capability for loading and storing long vectors in the long vector registers. Stride is not provided in these instructions, and if it is desired to load and store less than all 64 elements of the vector, an integer register from among registers 1, 2, or 3 must be used to contain the length. If the lR field contains a zero, all 64 elements of the vector are loaded or stored.
The Supplemental Memory-Reference instructions in lines 13 and 14 permit instructions to load and store values in additional data types supported by this architecture to be included in a limited form in the basic 32-bit instruction set.
The diagram below shows the format for 32-bit instructions which perform arithmetic operations, and which may affect the condition codes:
A three-address register-to-register operate instruction is shown in lines 1 through 3; either one of the source and operand registers may be replaced with pointers to pseudo-immediate operands. As the result of the instruction would be a constant if both of those operands were so replaced, this combination is illegal, and the bit pattern it would have is reserved for future expansion of the instruction set.
Two-address register-to-register operate instructions are shown in lines 4 and 5. These have a considerably larger space available for the opcode field, and, thus, are not restricted to the basic arithmetic operations provided for three operands.
Line 8 shows a two-operand register-to-register operate instruction that can use any of eight possible sets of condition codes, if the C bit is set, instead of just the normal set of condition codes. Like the flag bits used with instruction predicatiion, alternate sets of condition codes are a way to allow conditional branches to be delayed so as to reduce the need for branch prediction.
Lines 10 and 11 show register-to-register operate instructions that involve extended register banks, both integer and floating, with 128 registers instead of 32 registers. Larger register banks permit more operations to be performed before there is a need to re-use a register from which the result has been stored, reducing the occurence of hazards in pipelined code.
The mixed register two-address instructions in line 13 allow the large register banks to interact with the normal register banks.
The header formats of type III and IV provide for an alternate 32-bit instruction set, and a set of 33-bit instructions.
The 33-bit instructions have this form:
Lines 1 through 5 show memory-reference instructions in which the opcode field is increased from five bits to seven bits in length, so as to allow memory-to-register operate instructions. To compensate for this, the destination register field is reduced from five bits to three bits in length, which means that only registers 0 through 7 can interact wih memory in this fashion.
But since these are operate instructions, a condition code bit is in order, which is why these instructions have been classed as 33-bit instructions.
In addition, an indexed version of both the conditional jump instructions and the subroutine jump with offset instruction have been included in this group of alternate instructions.
The alternate 32-bit instructions have this form:
providing an indexed version of the multiple-register instructions, long vector load/store and supplemental memory reference instructions with longer opcodes, and register-to-register operate instructions with longer opcodes.
The header format of type IV, when the option bits in it are
set to 00, also provides for 35-bit instructions. These
instructions have the form:
allowing for memory-reference operate instructions that can have all 32 registers as their destinations.
In addition to the standard set of operate instructions, with seven-bit opcodes the first two bits of which are not both one, these instructions also include floating-point instructions for the Compatible floating-point format, in keeping with the functionality that has been prioritized elsewhere in instruction formats (the 53-bit instructions and the special 16-bit short instructions) made available by the header of Type IV.
Also, in Augmented Short Instruction Mode, the basic memory-reference instructionms are modified to make additional opcode space available; other 32-bit instructions are re-organized as well; the other memory-reference instructions are simply moved by having one bit changed, while the operate instructions gain longer opcode fields. The instruction set in this mode, except for the 15-bit instructions which replace the 14-bit instructions, shown on a later page, have the form:
The Subroutine Jump with Offset instruction is not available in this mode.
In this mode, if a basic memory-reference instruction is indexed, only registers 2 through 7, with register 1 excluded, may be used as its index register, and only registers 29, 30, and 31 may be used as base registers with 16-bit displacements, excluding registers 25 through 28. The base register used for 15-bit displacements and the base registers used with 12-bit displacements are unaffected.
In the case of a Type VI header, an X bit is available which can be used to call for an alternative version of this mode:
Here, the operate instructions are left as they are in the basic instruction set, without any increase in the size of their opcode fields, in order that a break bit can be provided for the second 15-bit instruction in a pair as well as the first.