The 17-bit instructions
are made available when a block starts with 1110; the
last sixteen bits of the instruction appear in their normal position in the
instruction stream, the first bit appears within the block header. This type
of block is termed a block with a header of Type II.
They are also made available by a number of other block formats, specifically the type III, V, and X formats.
The instructions to be described in this section have the formats shown in this diagram:
The diagram shows the different 17-bit instructions.
The 17-bit instructions do not include memory-reference instructions, or the subroutine jump instruction. However, while the set of 17-bit instructions is therefore not complete in itself, it is sufficient that a large proportion of the instructions in a program could be 17-bit instructions.
Line 1 gives the format of the operate instructions. Integer instructions reference the integer registers, and floating-point instructions reference the floating-point registers, as might be expected.
There are 96 possible opcodes, as the first two bits of an opcode may not be both 1, as these combinations are reserved for other 17-bit instructions.
The opcodes (with the first four bits appearing along the top of the chart, and the last three bits appearing on the right) are:
0 10 20 30 40 50 60 70 100 110 120 130
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
SWB IB SWH IH SW I SWL SWM SWF SWD SWQ 000 0
CB CH C CL CM CF CD CQ 001 1
LB ULB LH ULH L UL LL LM LF LD LQ 010 2
STB XB STH XH ST X STL XL STM STF STD STQ 011 3
AB NB AH NH A N AL NL AM AF AD AQ 100 4
SB OB SH OH S O SL OL SM SF SD SQ 101 5
MH MEH M ME ML MEL MM MF MD MQ 110 6
DH DEH D DE DL DEL DM DF DD DQ 111 7
The different instructions are:
For integer types:
M MULTIPLY Multiply the contents of the source and destination locations, placing the
least significant part of the result of the same length as the two input
operands in the destination location, with sign extension if that is shorter
than the length of the destination register
D DIVIDE Divide the contents of the source location by the contents of the destination
location, placing the quotient in the destination location
L LOAD Place the contents of the source operand in the destination register;
if the type involved is smaller than the register, perform sign extension
ST STORE Fill the destination location from the least significant part of the
source location
A ADD Add the contents of the source and destination locations, placing the
result in the destination location
S SUBTRACT Subtract the contents of the source location from those of the destination
location, placing the result in the source location
SW SWAP Exchange the contents of the source and destination locations
C COMPARE Subtract the contents of the source location from the contents of
the destination location, but with the operation modified so that
overflow cannot possibly result, and set the condition codes appropriately
without modifying the destination location
I INSERT Fill the least significant bits of the destination register with
the contents of the source location, leaving the rest of the destination
register unaffected
UL UNSIGNED LOAD Fill the least significant bits of the destination register with
the contents of the source location, and clear the remaining more
significant bits of the destination register
X EXCLUSIVE OR Perform a bitwise Exclusive OR operation between the contents of the source
and destination locations, placing the result in the desination location
N AND Perform a bitwise Logical AND operation between the contents of the source
and destination locations, placing the result in the desination location
O OR Perform a bitwise Logical OR operation between the contents of the source
and destination locations, placing the result in the desination location
ME MULTIPLY EXTENSIBLY Multiply the contents of the source and destination locations. Take the
full product, as an integer having twice the size as that of the source
and the destination, and:
- in the case of the halfword and integer versions of the instruction, place it in the destination
register, with sign extension in the halfword version;
- in the case of the long version of the instruction, place the most significannt half of the result
in the destination register, which must be an even-numbered register, and place the least significant
half of the result in the register following
DE DIVIDE EXTENSIBLY Divide a destination operand of twice the length of that indicated by the
instruction type (and located as the result of the MULTIPLY EXTENSIBLY
instruction) by the source operand; store the double length quotient
in the destination location (again following the MULTIPLY EXTENSIBLY
result placement) and the single length remainder in the next register
following those that are used.
Whenever a result is not wide enough to fill a register, sign extension
is performed.
Division is performed giving a result as if both operands were converted
to positive numbers before starting, with the signs then set afterwards
to give a correct result based on the actual signs of the operands. Thus
both the quotient and the remainder will be positive or zero if the dividend
and divisor have the same sign, and both will be negative or zero if they
are of opposite signs.
The possible integer types, and the suffixes that indicate them, are:
B BYTE An 8-bit two's complement integer
H HALFWORD A 16-bit two's complement integer
INTEGER A 32-bit two's complement integer
L LONG A 64-bit two's complement integer
The integer registers are 64 bits long, to contain the longest of these types.
The available floating-point operations are SWAP, LOAD, STORE, ADD, SUBTRACT, MULTIPLY, and DIVIDE. Their functions are basically the same as those of the corresponding integer operations, except that floating-point arithmetic is performed.
The possible floating-point types for 16-bit instructions, and the suffixes that indicate them, are:
M MEDIUM A 48-bit floating-point number (preferably aligned on 16-bit boundaries) F FLOATING A 32-bit floating-point number D DOUBLE A 64-bit floating-point number Q QUAD A 128-bit floating-point number
with their formats as indicated within this diagram:
Note that in the diagram, exponents for the types other than the 128-bit internal type are given as excess-126, excess-510, and excess-1022; documentation for the IEEE 754 standard, and most descriptions of it, refer to the exponents as excess-127, excess-511, and excess-1023 instead. This is because these accounts place the binary point of the mantissa in front of its first visible bit, while I place it in front of the hidden first bit to remain in accord with the convention used in most other floating-point formats that the mantissa is in the range [0.1). In the case of the 128-bit internal form, as the first bit of the mantissa is now the bit which would have been the hidden bit, since for the other forms, I had been placing the binary point in front of the hidden bit, the offset is consistent by remaining two less than a power of two; this would need to be the case even if I had used the normal convention for the exponents of the other formats.
Originally, it had been planned to have the 128-bit type of this architecture to be similar to 80-bit temporary real, but with a longer mantissa. In response to the new standard for a 256-bit floating type, what has been done is to make the exponent field of the 128-bit floating type of this architecture one bit larger than that of the new standard 256-bit floating-point type (in order to be able to handle its denormals correctly).
This means that instructions other than the short ones described on this page will be available to support the old 80-bit temporary real format, and the new standard 128-bit and 256-bit floating-point formats, but the internal form of a standard 128-bit floating-point number will require the use of more than one register, and the internal form of a standard 256-bit floating-point number will require the use of more than two registers.
These instructions are then also suffixed RC for Register Compact to indicate the addressing mode.
Lines 2 through 5 of the diagram illustrate the shift and rotate short instructions. These are:
300xxx LSLLC Logical Shift Left Long Compact
304xxx LSRLC Logical Shift Right Long Compact
310xxx RLLC Rotate Left Long Compact
314xxx ASRLC Arithmetic Shift Right Long Compact
320xxx LSLC Logical Shift Left Compact
324xxx LSRC Logical Shift Right Compact
330xxx RLC Rotate Left Compact
334xxx ASRC Arithmetic Shift Right Compact
322xxx LSLHC Logical Shift Left Halfword Compact
326xxx LSRHC Logical Shift Right Halfword Compact
332xxx RLHC Rotate Left Halfword Compact
336xxx ASRHC Arithmetic Shift Right Halfword Compact
3230xx LSLBC Logical Shift Left Byte Compact
3270xx LSRBC Logical Shift Right Byte Compact
3330xx RLBC Rotate Left Byte Compact
3370xx ASRBC Arithmetic Shift Right Byte Compact
Logical right and left shifts insert zeroes; the arithmetic right shift inserts a copy of the existing value of the most significant bit into the leftmost position of the word so as to maintain the sign as either negative or non-negative.
An arithmetic left shift inserts zeroes into the leftmost end of a number regardless of its sign, just like a logical left shift, but it differs in that the overflow bit is set if a left shift results in a change of the sign of the value being shifted, instead of merely a carry out of that value; this difference is, however, not applicable to short instructions, as they may not alter the condition codes, not having space for a C bit.
In the 16-bit short instructions, there is no available separate region of opcode space for the rotate instructions, and so instead the arithmetic left shift is replaced by rotate left.
Line 6 of the diagram shows the branch instructions.
The displacement is an 8-bit signed value, in two's complement form, which may vary from -128 to +127. The displacement is in units of 16 bits. No attempt is made to skip over values corresponding to the 32-bit instruction slots containing header information in counting; the displacement is an actual displacement in terms of the memory address, not a count of skipped instructions. A displacement of zero refers to the position immediately following the instruction. The target of a branch instruction must always be an actual executable instruction, and not a setup directive, an immediate value, or any part of a 48-bit or 80-bit instruction other than its first 16 bits.
The available branch instructions are:
3404xx BL Branch if Low
3410xx BE Branch if Equal
3414xx BLE Branch if Low or Equal
3420xx BH Branch if High
3424xx BNE Branch if Not Equal
3430xx BHE Branch if High or Equal
3434xx BNV Branch if No Overflow
3440xx BV Branch if Overflow
3450xx BC Branch if Carry
3454xx BNC Branch if No Carry
3474xx B Branch
Line 7 of the diagram of 17-bit short instructions, and the correspoonding line in the diagram of 15-bit short instructions, shows how condition values that are invalid result instead in an additional category of instructions which affect the flags used for predicated instructions.
3400xx CTF Condition to Flag Set flag to 1 if condition valid; set flag to 0 if condition not met
3460xx SFC Set Flag on Condition Set flag to 1 if condition met; leave it unaffected otherwise
3464xx CFC Clear Flag on Condition Set flag to 0 if condition met; leave it unaffected otherwise
Line 8 of the diagram of 17-bit short instructions, and the correspoonding line in the diagram of 15-bit short instructions, shows how an additional invalid condition value provides another special instruction:
3470xx SVC Supervisor Call
This instruction performs the equivalent of an interrupt from within software, allowing portions of the operating system not running in supervisor state to request services from the kernel, as well as possibly also allowing user programs to request services from the operating system.
14-bit short instructions are made available in instruction slots which start with
1111 so as to permit the use of short instructions without the need for a special
header.
The format of these short instructions is shown below:
As can be seen, they are very similar to the 17-bit short instructions.
One important change is that the shift instructions, in lines 2 through 5, can only operate on the contents of the first eight registers, registers 0 through 7.
The register-to-register instructions in line 1 are changed in two ways.
The first is that a two-bit page field is shared between the source and destination registers; it supplies the two most significant bits of the register number for both the source and destination registers, while the source and destination register fields supply the three least significant bits of the register number for those registers respectively.
This allows these register-to-register instructions to access all the registers, but the registers are divided into four groups of eight registers, and both operands of such an instruction must belong to the same one of these groups.
The second is that the opcode field is reduced to five bits in length, so only a select set of the most important operations can be performed by instructions of this form.
The table below shows the opcodes of the instructions that are available.
00 10 10 11 SW SWL SWF SWD 000 C CL CF CD 001 L LL LF LD 010 ST STL STF STD 011 A AL AF AD 100 S SL SF SD 101 M ML MF MD 110 D DL DF DD 111
The format of these short instructions is shown below:
This form of short instruction is available in blocks indicated as having instructions in Augmented Short Instruction Mode. These instructions combine the full-length seven-bit opcodes for operate instructions provided in 17-bit instructions with the form of source and destination register fields with shared bits used in 14-bit instructions.
These instructions are indicated by a Type V header with the
option field containing 00.
The format of these short instructions is shown below:
The purpose of these instructions, available with the Type IV header only, is to accompany the 35-bit and 53-bit instructions with 16-bit floating-point instructions that use the Compatible floating-point format. This floating-point format consists of a sign bit, a seven-bit exponent which is a power of 16 (rather than 2), and a mantissa.
Also provided in this format is the Save Return Address instruction, having a similar function to a jump to subroutine instruction with relative addressing and a displacement of zero.
In addition to the normal banks of 32 integer registers and 32 floating-point registers, this architecture offers extended register banks of 128 integer registers and 128 floating-point registers.
When VLIW capabilities are combined with variable-length instructions, the type X header contains a bit which switches to the use of an alternate form of 17-bit short instructions that makes use of the extended register banks, as they may be preferred for use in programs with an explicit indication of parallelism.
These instructions have the form:
In the first line, it is shown how access to all 128 registers is provided in an instruction that is only 17 bits long: the two registers used, as in 14-bit and 15-bit short instructions using the regular register banks, must belong to the same group of eight registers.
While the format of the shift instructions is not changed, now they refer to the first 32 integer registers in the extended register bank rather than all the integer registers in the regular register bank.
The format of these short instructions is shown below:
Their purpose is to facilitate the use of the extended register banks with VLIW features to permit greater effective use of the superscalar capabilities of a given implementation of the architecture.
This instruction type is only used with the type III header.
Instructions starting with 1 are the same as the
alternate 17-bit instructions after the prefixed 1.
The additional bit can also be 0, as shown in the first
three lines of the diagram, which provides the additional capabilities
of:
The format of these short instructions is shown below:
These instructions are similar to the 18-bit instructions, but are used with the type V header.
Here, instructions starting with 11 are similar to the
alternate 17-bit instructions, except for having the two bits added, and
only one new type of instruction is added, in the first line of the diagram,
an instruction that moves information between any two registers in an
extended register bank.