The lengths of the instructions longer than 32 bits are indicated by their first few bits as follows:
0111111 144 bits 11001 64 bits 1101xxx 48 bits 1101111 112 bits 11111xxxxx 80 bits 1111111100 96 bits 1111111101 160 bits 111111111 288 bits
The 48-bit instructions all begin with 1101, but a small amount of
space at the end of that range is allocated instead to the 112-bit instructions.
The formats of the 48-bit instructions are shown below:
Lines 2 through 5 show an instruction format which includes a B bit, for break, which, if cleared, indicates the instruction may be performed in parallel with the one that preceded it, a P bit, for predicated, which indicates the instruction is predicated, and an S bit, for sense.
The flag field selects a flag bit; if the instruction is predicated,
it is performed if the flag bit is set when the S bit is 0,
but it is performed if the flag bit is cleared when the S bit is
1.
In addition to including a normal 32-bit instruction, this type of instruction may include a pair of short instructions. Each one may have a six-bit opcode field if it is an integer operation, or a five-bit opcode field if it is a floating-point operation.
In the case where both short instructions are of the same type, an additional break bit is provided to indicate, if clear, that the two short instructions within the 48-bit instruction may be performed in parallel. In line 4, there is space for this bit between the two floating-point instructions; in line 5, it is placed ahead of the pair of integer operations, but it still signifies a break between those two instructions.
In line 3 of the diagram, we see that when one is a floating-point operation, and the other is an integer operation, since the two operations use a different ALU and a different register bank, it is assumed that they may always be executed in parallel, and the break bit is not provided.
It was stated that in line 2 of the diagram, the 32-bit instructions that may be predicated are normal 32-bit instructions. This is not quite true. As there is unused opcode space within them, due to the fact that instructions of lengths other than 32 bits aren't available in that position, this opcode space was slightly enlarged in order to allow a more versatile form of paired short instructions to be used in this position as well. The modification consisted of replacing the normal 32-bit Halfword Immediate instruction with a more limited form; it was described on the previous page which described the various forms of short instructions in this architecture (other than the ones shown on lines 3, 4, and 5 of the diagram above, which are described here).
This also applies to the embedded 32-bit instructions shown below for 80-bit, 112-bit, and 144-bit instructions.
Also, there is an important set of restrictions to be aware of if one is attempting to branch directly to the embedded 32-bit instruction instead of the 48-bit instruction that contains it. This will be explained in the section on 80-bit instructions.
Note that among the memory reference instructions shown in lines 11, 14, 15, and 16, there are memory-to-register operate instructions, which is why a C bit is present.
The formats of 64-bit instructions are shown below: in these instructions,
the first five bits are 11001, to indicate that the instruction is 64 bits long.
The formats of 80-bit instructions are shown below: in these instructions,
the first five bits are 11111, to indicate that the instruction is 80 bits long.
Lines 2 through 5 of the diagram illustrate an instruction format similar to that shown in lines 2 through 5 of the diagram of 48-bit instructions. Here, the two embedded 32-bit instructions may not be predicated, but each one still has a break bit, and in addition, they may be replaced with paired short instructions, which under some circumstances have an additional break bit between the two short instructions of the pair, as noted for the 48-bit instructions.
Note that there is an A bit in this instruction format. If this bit is set, it affects only the regular 32-bit instructions, not the paired 16-bit short instructions. It causes the load/store memory-reference instructions to be replaced by memory-reference operate instructions instead, with the following format:
These instructions may not affect the condition codes, and they may only have the first eight registers as their destination registers.
The Concertina IV architecture, unlike the Concertina II architecture, is not block structured. In the Concertina II architecture, programs are composed of instruction blocks which are 256 bits long, and aligned on 256-bit boundaries. Hence, when a branch to an instruction is performed, the header of the block in which it is contained can be read first, so that the instruction can be correctly interpreted.
When a 32-bit instruction is embedded in a 48-bit, 80-bit, 112-bit, or 144-bit instruction in the Concertina IV architecture, and an attempt is made to branch to that embedded 32-bit instruction, instruction interpretation begins at the target address of the branch; it is not possible to determine that the instruction is, in fact, embedded in a longer instruction, nor is it possible to determine where the instruction in which it is embedded begins.
As a result, there is no automatic guarantee that branching to an embedded instruction will be successful.
However, since the 32-bit embedded instructions are at the end of the instructions in which they are contain, it is possible for them to be branched to, and correctly interpreted, if the following conditions are met:
These restrictions, however, do not apply when the Jump to Embedded instruction is used, as it has the location of the larger instruction containing other instructions as its effective address, then identifying the embedded instruction to which control is to be transferred by means of its offset field. This entirely avoids the difficulty imposed by being unable to locate the start of the larger instruction, since exactly that location is directly specified.
The formats of the 96-bit, 160-bit, 288-bit, and 144-bit instructions are shown below.
Lines 4 through 7 of the diagram give the format of a 160-bit instruction, which has 32 bits of overhead rather than 16, thus allowing the four embedded 32-bit instructions within it to be predicated, as well as replaced by paired 16-bit instructions and given an explicit indication of parallelism.
Each of the four embedded instructions has a P bit associated with it,
to indicate, if that bit is 1, that it is predicated, but all four instructions
share the same S bit and flag field, to indicate which of
the sixteen flag bits controls whether or not a predicated instruction is executed, and
whether it is executed when the flag bit is set (in the case of the S bit
being 0), or when it is cleared (if the S bit is
1).
In lines 6 and 7, as noted for the 48-bit instructions, an additional B or break bit is shown which is associated with the second short instruction in a pair.
Since store immediate instructions are not valid, the opcode space is available for the instruction format shown in line 10. Here, a break bit is made available for four embedded instructions, but the paired short instruction formats with 5-bit register specifications are not available. However, as with the 48-bit, 80-bit, and 112-bit long instructions with embedded 32-bit instructions, the Halfword Immediate instruction is modified and the paired short 15-bit instructions are available.
The same restrictions as outlined in the section concerning the 80-bit instructions apply as well to attempts to branch to an embedded instruction within an instruction in both of these formats.
Note also that the 144-bit instructions in line 10 of the diagram include an A bit, which has the same significance as the one in the instructions shown in lines 2 through 5 of the diagram of 80-bit instructions. There is, on the other hand, no room for this bit in the 160-bit instruction format shown in lines 4 through 7.
Line 8 shows the format of the 288-bit instructions; these are immediate instructions for 256-bit constants.
And, finally, the 112-bit instructions have this form:
allowing three pairs of short instructions with full register specifications to be used with only 16 bits of overhead between them, as well as allowing parallelism to be indicated for three instructions.
The same precautions apply to branching to the instructions embedded within these instructions as were described in the section on the 80-bit instructions.