Looking at 24 Bits

A fundamental unit of 12 bits allows items of 36 bits, 48 bits, and 60 bits in length to be addressed. But a 12-bit wide data bus is needlessly slow, and attempting to confine most instructions to a 12-bit word is also limiting.

Back when the speed of computer memories was comparable to that of the arithmetic unit in the CPU itself, so that computers tended to have a single accumulator rather than several general registers, a 24-bit instruction word had enough room for a six-bit opcode, a fifteen-bit address (reaching 32,768 words of memory), and three extra bits for addressing modes.

Is it possible to bring the 24-bit word into the modern era of computing?

The illustration above shows an example of an instruction word format intended to address these goals.

Instead of 64 possible 6-bit opcodes, in the diagram the possible instructions are divided into 48 with 6-bit opcodes, with the formats in the last six lines of the diagram, and 112 with 9-bit opcodes, with the formats in the first four lines of the diagram.

Instead of having one bit to specify indirection, and two to specify an index register, as in many classic 24-bit computers, one bit indicates if the next two specify one of four general registers as the destination of the operand, or an index register; in the latter case, register 0 is the destination.

Since 100 would be a duplicate of 000, destination register 0 without indexing, given the convention that specifying index register 0 means no indexing, it is used instead to indicate additional addressing modes.

Given four general registers, it is possible to fit two register-to-register instructions in a single 24-bit word, and that is perhaps the most important additional mode to add.

Using an address field of only 12 bits, so that the destination has to be more local, indirect addressing can be added. Plain indirect addressing is indicated by zero in the index register fiels. Pre-indexed indirect addressing is selected by a bit that is unused when putting two register-to-register instructions in a word.

RISC-like instructions can be squeezed in because of the limitation on the range of the 6-bit opcodes. The four general registers are the first of the 64 registers, to allow data to go in and out of those registers without adding additional instructions.

In the case of the instructions with 9-bit opcodes, since both indirect addressing and RISC-like instructions are highly desirable, but there is only room for one of them made by index register zero, so room is made for the other mode by reducing the number of 9-bit opcode instructions by 16, from 128 to 112.

Address constants could be 48 bits long, beginning with an index bit and followed by two bits which, if nonzero, indicate indexing and specify the index register used. A 45-bit address is comparable to the address buses actually used with many devices using 64-bit addressing.

Dividing memory into 32K and 4K pages avoids the need to perform an addition when generating addresses if indexing is not used, although this is a technique generally abandoned after the early era of computers. It does have the desired modern effect of encouraging locality of reference.

The 48 instructions with six-bit opcodes could include 16 instructions for each of two integer types and 8 instructions for each of two floating-point types. If the integer types are 24 bits and 48 bits long, and the floating-point types are 48-bit intermediate and 96-bit extended, the 15-bit address fields might as well be displacements in units of 24-bit words.

Among the 112 instructions with 9-bit opcodes would be the integer instructions operating on 12-bit halfwords and the floating-point instructions operating on 36-bit single precision numbers and 60-bit double precision numbers, so the 12-bit address fields would be displacements in units of 12 bits. Thus, index register contents and address constants would also be in units of 12 bits, these being the basis of addressing.

Indirect addressing, although a holdover from an earlier era, allows instructions to, in effect, be longer than 24 bits without having to complicate instruction decoding by having instructions of different lengths. And this also helps to make it possible to cope with the division of memory into pages of 32K or 2K words.

Given the limitation to 112 instructions with 9-bit opcodes, words with the first eight bits all ones won't be used for the scratchpad format, so these can be used for instructions that operate on the contents of a single general register, such as shift, absolute value, and negate, following the same principle as the operate instructions with opcode 7 on the PDP-8.