To illustrate how a computer works, some examples of computer architectures will be illustrated here. The next section will show an imaginary design with a 24 bit word length. That word length was chosen because it allows a simple format for instruction words along with a memory of moderately large size (32,768 words) and a moderately complex repertoire of instructions (hardware floating point in both single and double precision).
But to begin, it would seem appropriate to begin with as simple a computer architecture as possible. That does not necessarily mean a very small computer; a computer with a 24-bit word was chosen in the next section specifically to avoid having to deal with the complexities that result when an instruction word does not have enough room to contain a complete memory address.
Of the early stored-program computers, the IBM 701 Defense Calculator is one that had random-access memory, although implemented with Williams tubes and not core, and which had a particularly simple and straightforwards instruction set.
It represented numbers internally in sign-magnitude format, rather than in the two's complement notation that is currently popular.
The memory consisted of 2,048 words, each 36 bits in length, but the machine could address and operate on individual 18-bit quantities. When an 18-bit number is loaded into the machine's accumulator, for consistency in handling carry and overflow, it is loaded into the most significant part of the accumulator; this means that one cannot convert integers simply by loading them in one format and storing them in another.
Incidentally, with sign-magnitude notation, carry out of the magnitude portion of the number constituded an overflow, so the overflow bit was considered to be placed between the sign bit and the magnitude bits of the conventional quantity in the accumulator.
Instructions in the IBM Electronic Data Processing Machine, Type 701 (which was never called an EDPM-701 by IBM, unlike the Digital Equipment Corporation Programmed Data Processor-8, also known as the PDP-8, or the Computer Controls Corporation Digital Data Processor-224, also known as the DDP-224... not to mention the BESM-6) all had the format shown below:
The bit marked T indicated an 18-bit operation, if it was 0, and a 36-bit operation, if it was 1. Since this was also the sign position, this led to the convention that positive addresses stood for halfwords, and even negative addresses stood for words. This was perhaps the only thing about the design that was too clever by half: instead of simply using another bit to specify type, this suggests that if the architecture were extended to include hardware handling of 72-bit double-precision floating point numbers, imaginary numbers would be needed to address them. (Incidentally, I am quite sure this particular jibe is not original with me, although I can't remember exactly where I heard it before.)
Unlike the PDP-8, however, this architecture was not kept around to be extended out of all recognition compared to its humble origins; its immediate successor, the IBM 704, had a very similar-looking front panel, and it did have hardware floating point, but it had a completely different instruction format.
And what were the instructions of the IBM 701?
Excluding input-output operations, they were:
00000 STOP Stop and Transfer Halt; restart address = addr 00001 TR Transfer Jump to (addr) 00010 TR OV Transfer on Overflow if overflow, jump to (addr) 00011 TR + Transfer on Plus if ACC greater than or equal to 0, jump to (addr) 00100 TR 0 Transfer on Zero if ACC = 0, jump to (addr) 00101 SUB Subtract ACC = ACC - MEM(addr) 00110 R SUB Reset and Subtract ACC = 0 - MEM(addr) 00111 SUB AB Subtract Absolute Value ACC = ACC - ABS(MEM(addr)) 01001 ADD Add ACC = ACC + MEM(addr) 01010 R ADD Reset and Add ACC = MEM(addr) 01011 ADD AB Add Absolute Value ACC = ACC + ABS(MEM(addr)) 01100 STORE Store MEM(addr) = ACC 001101 STORE A Store Address MEM(addr)[6..17] = ACC[6..17] 101101 EXTR Extract MEM(addr) = MEM(addr) AND ACC 01110 STORE MQ Store MQ MEM(addr) = MQ 01111 LOAD MQ Load MQ MQ = MEM(addr) 10000 MPY Multiply [ACC,MQ] = MQ * MEM(addr) 10001 MPY ROUND Multiply and Round MPY then ROUND 10010 DIV Divide MQ = [ACC,MQ]/MEM(addr); ACC = remainder 10011 ROUND Round if MQ high bit set, ACC = ACC + 1 10100 L LEFT Long Left Shift shift [ACC,MQ] left addr places 10101 L RIGHT Long Right Shift shift [ACC,MQ] right addr places 10110 A LEFT Accumulator Left Shift shift ACC left addr places 10111 A RIGHT Accumulator Right Shift shift ACC right addr places
Note that the instruction with opcode thirteen would up being more complicated, performing a completely different instruction if its operand was halfword or fullword. And the IBM 701 was the first of a long line of IBM computers whose first digit was a 7.
If someone at IBM wasn't superstitious, perhaps it was merely their commercial clients they were concerned about. Which is better than following the example of English Electric, which tried to sell a computer it called the DEUCE. It may also be noted that the Extract instruction wasn't originally present in the design, but was added in a revision to the computer's manual, making this a bizarre coincidence, perhaps.
In any event, this computer had operations with which it could do all the obvious things. It had the Extract operation for bitwise logic, which was also useful for masking out bits over an area of memory; it could do all the standard arithmetic operations.
It did not have a special instruction for looping, but this chore could be trivially handled by using the addition and conditional branch instructions.
More alarmingly, it is missing any kind of subroutine jump instruction. This isn't absolutely fatal. One can, before jumping to a subroutine, store the return address in some standard location explicitly. But because that affords an opportunity for error, most subsequent architectures did include such instructions. The Store Address instruction, however, would assist in modifying the address portion of a jump used to return from a subroutine.
As we will see later, the PDP-8, having only six opcodes available for memory-reference instructions, used one for a loop instruction (ISZ), and another for a subroutine jump (JSR), despite not being able to include both a load and a store instruction: instead, the store instruction was replaced by one that cleared the accumulator after storing it in memory (DCA) so that the addition instruction (TAD) could also serve as the load instruction. It also had an unconditional jump (JMP) and one logical operation (AND). Thus, a loop instruction, and a subroutine jump instruction, missing here, were subsequently given a very high priority.