Today, modern microcomputers make use of a stack to save the address to which to return after a subroutine jump.
Thus, on the Motorola 6800, the JSR instruction placed the return address on the stack, decrementing the stack pointer register by two, and branched to the target of the instruction.
The PDP-11 was not, by any means, the first computer to have a stack (the KDF 9 and several machines by Burroughs long preceded it) but it was a very influential machine, inspiring many of the characteristics of today's microcomputers.
The JSR instruction on the PDP-11 had one normal operand field with an addressing mode and a register, for the destination of the jump, and one field with a register specification only. That identified the linkage register, in which the return address was stored.
However, before the return address was stored in that register, its former contents were placed on the stack, register 6 being the stack pointer on the PDP-11.
This, compared to the pure stack method of the 6800, seems to use up the linkage register for no reason, but it may have made subroutine return more efficient (as popping the stack could take place on a pipeline at leisure, not being a prerequisite for returning from the subroutine) or it may have avoided the need to use extra circuitry for a temporary buffer for the return address.
Before the PDP-11, there was the IBM 360, which was itself very influential in inspiring the word length and character size of the PDP-11.
The System/360 used the Branch and Link (BAL) instruction to call a subroutine.
This instruction branched to the effective address of the source operand, and stored the return address in the destination register. The return address was accompanied by other information, the low 32 bits of the PSW being stored, and addresses in the original System/360 being 24 bits long.
There was also a BALR instruction; that one branched indirectly to the address indicated by the contents of the source register. However, if register 0 was specified as the source register, no branch took place (somewhat by analogy of the rules applying to index and base register specifications); this allowed a BALR n,0 instruction to be used by the computer to find out what location the program was currently running at; this was useful in setting up base registers when a program started running.
Before the System/360, when instructions typically involved one memory location and the accumulator, and computers didn't have general registers, even if they might have more than one index register, there were two popular types of subroutine call instruction.
One was the type used with the PDP-8.
The JMS instruction on the PDP-8 stored the return address at the location pointed to by the effective address of the instruction, and then branched to the following word.
This meant that subroutines could not be located in read-only memory, and it made having re-entrant subroutines difficult, and thus this type of subroutine call horrifies people today.
The other was the type used with the IBM 704 and its successors.
The TSX instruction used the index register field of the instruction to indicate which index register would be used to store the return address. (In fact, the two's complement of the return address was stored there, since when indexing was used on these computers, the index register contents were subtracted from the address instead of added. If that wasn't confusing enough, normal fixed-point arithmetic on the 704 used sign-magnitude format.) The effective address, exclusive of indexing, was to where control would be transferred.
The Honeywell 116, 316, 416 and 516, not surprisingly, followed the PDP-8 method with their JST instruction, as did the Hewlett-Packard 2114A, 2115A and 2116A with their JSB instruction.
Among computers with 24-bit words:
The SPB (Store Place and Branch) instruction of the Systems Engineering Laboratories 840 simply followed the PDP-8, storing the return address at the target location and then transfering control to the one following.
The Scientific Control Corporation 660 followed the PDP-8 with its BSL instruction, however some additional information was stored in the more significant portion of the target word before the return address, which only took up the least significant 24 bits.
The Computer Control Company DDP 24, and its successors by Honeywell, followed the PDP-8, but it only modified the last 15 bits of the target word, leaving the preceding portion unchanged. This meant that if a jump instruction was placed there, return from the subroutine could be effected by branching to that location, instead of using an indirect jump instruction. The RTJ instruction of the ASI 6020 computer also worked in this way.
The Datacraft DC 6024, and the Harris Slash/4 and related machines that followed it, offered a choice. There was a Branch and Link instruction that could store the return address in one of the three index registers, and there was also a Branch and Save Return instruction that stored the return address at the location to which the instruction pointed, branching to the following location, so both the 704 and PDP-8 schemes were available.
The SDS 920, 930, and 940 computers had a BRM instruction, which also followed the PDP-8 scheme.
The SDS 9300 computer, however, offered the programmer another type of choice.
It, too, had a BRM instruction that followed the PDP-8 scheme. However, it stored the address of the BRM instruction itself at the destination; there was a BRR instruction that incremented that address first before branching to it.
It also had a BMA instruction. That instruction stored an address constant at its effective address that had the indirect address bit set, and the index bits cleared. (Flag information was stored in the bits that would have been opcode bits for an instruction as well.) This one stored the address of the location following the BMA intruction there, however, it was still intended that the BRR instruction would be used to return from the subroutine.
The intent of the BMA instruction was to allow that instruction to be followed by a pointer to an argument list for the subroutine, before the next instruction of the program.
Returning to computers of other word lengths:
Even the Control Data 1604 followed the PDP-8 when executing its Return Jump instruction. The IBM 1130, with its BSI instruction (Branch and Store IAR) also followed the PDP-8 style of subroutine jump.
The Univac 1103, because it was a two-address machine, had a Return Jump instruction that seemed like it belonged to the PDP-8 type, but avoided its pitfalls. The return address was stored at the destination address of the instruction, while the jump was taken to the source address of the instruction. So subroutines in ROM and subroutines with multiple entry points do not present problems with this kind of subrotine jump instruction.
The GE-235 computer effectively followed the IBM 704, although its index registers were locations in memory, usually locations 1, 2, and 3, although an optional feature allowed the computer to switch between several alternate sets of index locations in memory.
The PDP-6, and thus the PDP-10, with multiple general registers, saved the return address in a selected register, as the IBM 360 later did with the JSP instruction. The JSR instruction saved the return address in a memory location instead, and there was also the JSA instruction: this instruction saved both the return address and other information in a selected register, but depended on 18-bit addresses being adequate.