[Up] [Previous] [Next] [Next Section]

The Old Days: Computing Without RAM

In a modern computer, main memory is typically composed of cells which store a single bit which are composed of a single transistor and a capacitor. The transistor allows the memory cell to be addressed, and the capacitor stores the data in the form of an electrical charge. This type of memory is known as DRAM, for Dynamic Random Access Memory, because the contents of memory have to be periodically read and rewritten.

In the days of mainframes and minicomputers, magnetic cores were used for memory instead. The magnetic core itself served as an active element, as it was so designed that it would only be disturbed when pulses were sent through both of the two addressing wires that went through it. Sensitive amplifiers detected the electrical signals produced when the magnetization of a core was changed.

Before core became available for computer memories, the first form of random access memory for computers was the Williams tube. It was a storage-tube CRT which had the property that an electron beam aimed at its face could produce a signal indicating whether or not a previous beam had caused that spot to glow. It required refreshing, and was subject to a problem known as pattern sensitivity, but as the first practical form of random access memory, it increased the power of computers tremendously.

The active devices from which the logic elements which compose a computer are built, whether transistors, vacuum tubes, or even relays, can of course be used to construct a random-access memory consisting of flip-flops. The cache memory of a microprocessor, composed of cells consisting of perhaps four or six transistors, is of this kind. While a limited number of registers to contain the numbers a computer is working with could be built that way, building a memory large enough to hold a large array of data, or the program being executed itself, would have been an impossible extravagance.

What could be done?

The Harvard Mark I computer read a paper tape to obtain the steps of its program. Additional paper tape readers had tapes containing input data, or tapes which encoded function tables in a special notation designed to permit interpolating between table values.

The ENIAC, which used vacuum tubes instead of relays, was programmed by wiring patch cords from one arithmetic unit to another within the computer. Banks of switches were used to store tables of numbers that did not have to be changed during a computation.

The early stored-program computers still did not have random-access memory, but they did have electronic memories. One kind was the delay line. Sound waves, generated piezoelectrically, could travel through a trough of mercury. A slower, and less expensive and tidier, delay line was the magnetostrictive delay line, involving sound waves travelling through a special type of wire.

A particularly convenient option was the drum memory. Usually equivalent to a head-per-track disk, it allowed information to be stored on many parallel magnetic tracks, and each item of data became available to the computer once for each rotation of the drum.

Drums were also used as paging devices on computers with core memory, and the Univac 1103 computer had an address space which included both locations in random access memory (at first Williams tubes, then later core) and on the drum.

In the early days of the microprocessor revolution, shift-register chips were used as the memory for video display terminals, since they were both less expensive, and had larger capacity than, the available semiconductor RAM chips.

To put things in perspective:

The ENIAC was in operation by 1944, using switches to store constants, wiring for the program, and vacuum tubes to calculate.

The SSEC was in operation by 1948, using a special wide paper tape for the storage of intermediate results, having a small electrical memory in addition to doing its calculations electronically.

The Card-Programmed Calculator, which used punched cards to direct calculations, a small vacuum-tube memory for a few numbers, and plugboards for short, fast subroutines, dates from about the same period. As late as 1957, the IBM 610 was a machine with similar capabilities: short, fast subroutines on a plugboard, the main program on paper tape, and a small drum memory for intermediate storage of numbers only. (One could make a case that a Tcl/tk program, executed interpretively, to handle the user-interface, acting as a shell for a small program, written in C, is an embodiment of the same principle; the overall logic, that interacts with the user, can be slow, and only the repetitive loops that do the actual work need to run at the computer's full electronic speeds.)

The Manchester Mark I computer, the first computer with an electronic random access memory using the Williams tube, was in operation in 1949.

The UNIVAC I was delivered to customers in 1951, with a mercury delay-line memory.

Also in 1951, the ERA 1101 was announced. This machine, with a drum memory, soon became the Univac 1101 whan Univac acquired Engineering Research Associates.

It was also in 1951 that Whirlwind, the experimental computer that was the first one to use core memory, first was operational.

The first IBM 701 computer, with random-access Williams tube memory, was installed, replacing the SSEC at IBM headquarters, in 1952.

The Univac 1103, another computer with Williams tube memory, became available to the public in 1953.

The IBM 704, with hardware floating-point as well as core memory, was first delivered in early 1956; the IBM 705, a commercial machine with core memory, was delivered in late 1955; the two machines were announced together in 1955.

The IBM 650, a less-expensive computer with drum memory, was first delivered in late 1954.

The Univac 1103A, with core memory, and optional hardware floating-point, dates from 1956, as does the Ferranti Mercury, a British computer with core memory and hardware floating-point.

The first Datamatic D-1000 was installed in 1957, a vacuum tube machine with core from Honeywell.

In 1957, the first DEUCE, a computer with mercury delay-line memory, was delivered to customers in Britain. This computer was considerably less expensive than contemporary machines with core memory; as the Ferranti Mercury indicates, it does not indicate that the British were far behind.

The Packard-Bell 250, an inexpensive transistorized computer using magnetostrictive delay lines for memory, came out in 1960.

Thus, the transition from serial-access memories to random-access memories was a gradual one. Computers with Williams tube memories, because they had limitations of reliability, are still considered to be among the early computers. Drum memory in particular survived a long time because it was both inexpensive and reliable.

Although a computer which uses vacuum tubes for its logic gates seems very old-fashioned to us today, a computer such as the IBM 704 must still be counted as a "modern" computer. It had a relatively large (up to 32 K words, each 36 bits long) and well-behaved random-access memory, and a powerful instruction set.

The large transistorized computers from IBM and Univac, the Stretch and the LARC, were already being designed even before the first IBM 705 was delivered. But the Stretch was first delivered only in 1961, and the transistorized successor to the IBM 704, the IBM 7090, was first delivered the year before that, in 1960.

The Philco 2000 and the Control Data 1604, among the contenders for the honor of being the first transistorized computer, date from 1959.

Thus, computers with core memory and vacuum tube logic reigned for about five years, and those with discrete transistors for logic ruled for another five years, before the integrated circuit took over. But drum memory in particular maintained a strong presence even after core became available because it permitted less-expensive computers to be constructed.

The transition from discrete transistors to integrated circuits was also gradual.

The IBM 360, announced in 1964 and delivered in 1965, initially used integrated circuits, but of a transitional type where tiny chips containing individual transistors were fabricated into a module. The first System/360 computer to use monolithic integrated circuits for its CPU was the Model 85, which was announced in 1968 and first delivered in 1969.

Other computer makers waited to make the transition directly to monolithic integrated circuits. For example, not only the bulky PDP-5, but the PDP-8 and even the compact PDP-8/S having the usual minicomputer form factor (19-inch rack mountable, under a foot high) were all made with discrete transistors; the PDP-8/I, which came out in 1968, used MSI, medium-scale integration, in its circuitry. The transition came later for their larger computers: the PDP-6 (from 1964) and the original KA-10 chassis of the PDP-10 (from 1967) were discrete transistor machines, but the KI-10 of 1972 used integrated circuits.

Some of the mini makers tried harder to use advanced technology as a selling point for their computers; thus, the SDS 92 was announced in 1964, and although it made some use of discrete transistors, it made extensive use of integrated circuits; earlier, the SDS 910 was billed as the first transistorized computer to use only silicon semiconductors (meaning, no germanium transistors or even diodes) and the SEL 810 was another one of the first integrated circuit computers.

The advantages of core memory over serial memory were counterbalanced by higher cost, and integrated circuits only gradually gained a cost advantage over discrete transistors, which, with careful packaging, could be only marginally bulkier than small-scale integration ICs. But the advantages of transistors in bulk, power consumption and reliability over vacuum tubes were sufficiently compelling as to make that technological transition rapid instead of gradual.

A Simple Case: The IBM 650

The IBM 650 was a vacuum tube computer with drum memory which made it possible for many companies to make the transition from using such punched card equipment as sorters and tabulators to computers.

Although an affordable computer by the standards of its day, it still included some advanced features. Multiplication and division were performed in hardware. As searching a table for a value was a common operation which would be made particularly awkward on a drum computer due to its timing constraints, a special table lookup instruction was provided.

Instructions had the form:


where oo indicated the two digits that were the opcode of the instruction, ssss was the address of the memory operand, and nnnn was the address of the next instruction to execute.

Including the address of the next instruction to execute with each instruction was done because different instructions took different amounts of time to execute, and therefore it was advantageous to place the instructions on the drum so that the next instruction would be ready to be read just as the previous instruction had finished.

A More Typical Drum Computer: The Bendix G-15

Another relatively inexpensive computer built with vacuum tubes and using a drum memory that was very popular was the Bendix G-15. It was aimed at the scientific and engineering market. It was not quite as simple to understand as the IBM 650. Its instructions had the form:


where c was the single digit that indicated the opcode of the instruction if it was a two-address instruction.

Addresses on the drum were divided into a track portion and a sector portion. The nn field contained two digits which indicated the sector address of the next instruction to execute. Since the same sector on each track of the drum passed by the read heads at the same time, it really was only necessary to specify the sector address most of the time to allow programs to be optimized; the track address of instructions could remain constant, unless changed by a branch instruction.

The tt field contained two digits which indicated the sector address of the memory operands of the instruction. And the ss field contained the track address of the source operand, and the dd field contained the track address of the destination operand.

No, that was not a typographical error. The reason tt is used for a sector address, and ss is used for a track address, is because those fields were designated by T and S respectively in the documentation for the computer. Of course, it wasn't quite as strange as it sounds, because while S was a track address, it was the track address of the source operand, and D was used for the track address of the destination operand. Naturally, having a single sector address, but two different track addresses, allows both operands of an instruction to be present at the same time. Presumably the write heads on the drum were located at a position a suitable angle past the read heads, so that a calculation could be performed on the source operand, and the result stored in the destination operand, without waiting for an extra rotation of the drum.

Information could be transferred from one sector position to another, of course, by retaining it in the computer's accumulator, but this notation permitted a compact representation of programs and also encouraged writing programs that executed quickly.

The UNIVAC I Computer

This computer had 1000 words of memory. Each word consisted of 12 printable characters, each of which could have one of 63 possible values. Thus, it had a 72-bit word. These words also were used as signed 11-digit numbers, so it performed arithmetic directly on decimal digits in character form.

Each word contained two instructions. The instructions had a single address. Programmers had the option of using a jump instruction in the second position of each word used for a program to minimize latency; otherwise, words executed in sequence. The penalty for straight-line coding was limited, because the UNIVAC I computer used a large number of delay lines, so that each delay line contained only 10 words of memory.

The Very Devil of a Computer: Alan Turing's DEUCE

Made commercially available in England at about the time the UNIVAC I computer was available in the United States, the DEUCE was also a computer that made use of mercury delay lines.

The DEUCE was a computer that took some getting used to.

Instructions moved data between 32 locations in the computer; some of these locations were delay lines, and others were arithmetic units. Thus, the computer multiplied or divided when numbers were sent to the two inputs of the multiplier, and a number is taken from the output of that unit.

It contained the following complement of delay lines:

 4 which contained  1 word   (13 - 16)
 3 which contained  2 words  (19 - 21)
 2 which contained  4 words  (17 - 18)
12 which contained 32 words  (1 - 12)

Each instruction connected one source to one destination. The instructions also specified the delay line and the timing for the next instruction to execute, thus providing the complete address for the next instruction within the machine's main storage. There were also several modifier fields in the instruction. The delay lines were all kept synchronized, so that one word went past on any delay line in the same time.

The twelve delay lines with 32 words each constituted the main storage of the machine. Data words were 32 bits in length, representing numbers in two's complement binary notation.

The machine also had a drum with a moving block of 16 heads. It had 256 tracks. Each track contained 32 words of data, and the drum rotated at a speed corresponding to one-ninth of the cycle of a delay line with 32 words, so interleaving was used to allow data to be transferred from one track of the drum to one of the long delay lines of the computer.

As can be imagined, a great deal of care was required when writing programs to operate on data when it became available. That arithmetic operations were performed by connecting to special destination and source locations was something also done by much later computers with microprogram-like instruction sets (i.e., the GRI-909 or the Control Data Cyber computers) and also contributed to making programming the machine more difficult to learn.

The Pegasus

The Pegasus computer was an early computer with magnetostrictive delay line memory. The Pegasus 2 computer, specifically, had 16 delay lines which were 8 words long, a drum with 71 tracks, each containing 128 words, and there were 48 registers which contained one word each. The speed of data moving on the drum was the same as that of the speed of data movement in the delay lines, and individual words of data were directly read from, or written to, the drum.

This computer is credited with originating the concept of having general registers in a computer. In addition to having 48 single-word memory locations available for random access, it also had seven accumulators, and these accumulators also served as index registers.

Instructions were 19 bits in length, two of them fitting in a 39-bit word with one bit left over. A typical instruction would perform an operation between a register indicated by a 5-bit address, some having special purposes, and the accumulator. Another instruction format was used to transfer information between one of seven accumulators and memory, making it a load-store machine like today's RISC architectures.

As for optimum coding, an instruction called a block-transfer instruction was used to take a group of eight words from memory, and put them in a special set of short delay lines from which instructions to be executed directly were taken. So only one instruction in each group of sixteen had to be used to specify where further instructions should be coming from.

Causing computations to take place between the accumulators and the registers, and buffering the instruction stream in this manner, reduced (but did not eliminate) the impact of cyclic memory on programs.

The Packard-Bell 250 Computer

The Packard-Bell 250 computer was one of the earliest inexpensive computer systems, built with transistors, not vacuum tubes. It used magnetostrictive delay lines for its memory. It had ten delay lines containing 256 words of data, and a fast-access line containing 16 words of data. It also had an index register, and registers A, B, and C.

Instructions consisted of one operand and a memory address for an operand. The next instruction, except in the case of a branch instruction, could only be in one of two places; the next location after the current instruction, or the optimum position, determined by the location of the operand and the nature of the instruction, and on the same delay line.

The Selective Sequence Electronic Calculator

IBM's Selective Sequence Electronic Calculator was a unique and unusual machine. There is a considerable amount of general information available about the machine, as it was well-known in its day, and helped establish the popular image of computers as large and powerful devices. Because the machine was only used within IBM itself, more detailed information about its operation is not available from the types of sources that might first come to mind; however, it is described in great detail in the 350-page long U.S. patent 2,636,672.

It used vacuum tubes to perform arithmetic; it was able to directly add and subtract 19-digit numbers, and it could multiply two 14-digit numbers together to produce a 28-digit result, or divide a 28-digit number by a 14-digit divisor to produce a 14-digit quotient. But it used relays for the simpler functions of routing data from one place to another within the computer.

Normally, programs for the computer were directly executed as they were read from a card reader; each punched card contained two 20-digit numbers, each of which was a program step, along with having space on the card used for comments that identified the program to which it belonged and the card's place in the program. Two card readers were attached to the machine.

There were eight registers, each storing a number, made from vacuum-tube flip-flops within the computer. A larger random-access memory made from relays stored 150 numbers.

It used an unusual form of paper tape as its large-capacity storage.

The paper tape had the same width as an IBM card, and contained punches exactly like those on an 80-column card. As the tape had sprocket holes on its edges, there was room for 78 punches in a row.

Digits were encoded in natural BCD, or 8421 code. 78 punches provided room for 19 digits, When numbers were stored, two of the punches were used for the sign; one was always punched for a + sign, and the other was always punched for a - sign. When program steps were stored, those two punches indicated a digit that could be 0, 1, 2, or 3; this was the "s" field of the first operand in the instruction, and the limitation on its values corresponded to the fact that of the three operands to an instruction, the first had to be a source operand, while the remaining two could be either source or destination operands.

The SSEC had three working-storage units, each of which consisted of one paper tape punch, followed by ten paper tape readers. So, intermediate results could be punched in one of those units, and then re-read, in sequence with other results punched on that unit, up to ten times during the course of a program.

There were an additional thirty-six paper-tape readers to which loops of paper tape, punched before a program was started could be attached. These were normally used for tables of numbers. But they could also be used for subroutines, which was very important, so that if there was a loop in a program, the cards didn't need to be fed repeatedly into the card reader by hand. Apparently, it was also possible for the flow of control to be directed to the paper tape readers in the working-storage units as well; this has led to the claim by some recent historians that the SSEC was the world's first stored-program computer.

I would have thought that this capability was not used in practice, but the contemporary article giving the clearest description of the SSEC, Electrons and Computation by W. J. Eckert in the November, 1948 issue of The Scientific Monthly states:

In fact, the machine can compute detailed instructions as it goes along from general outlines presented to it.

b) Each line of instruction carries with it a number instructing the machine where to look for the next command. This command may depend on the result of a computation just completed.

What this means is, of course, ambiguous, and may refer to nothing more than conditional branching.

The format of an instruction in the SSEC, as shown on a punched card, consists of three addresses, each one five digits long, divided into a one-digit "s" field, a one-digit "b" field, and a three-digit "r" field; one digit indicating a shift; two digits giving the "operation", and two digits giving the "sequence".

The s field for the first address can only be 0, 1, 2, or 3. This allows an instruction to fit into the 78 punches on a row of tape. This did not limit the machine, because those values of the s field correspond to fetching a number from the source indicated by the three-digit r field, and at least one operand would be taken from storage in any instruction. Having different values for the s field allowed it to be specified that the sign of an operand was to be changed. The b field indicated the bus to be used for the operand. If the r field was not used to indicate a source or destination, the b field indicated one of the eight fast flip-flop registers.

The possible meanings of the s field are:

0 source operand, take absolute value
1 source operand, invert sign
2 source operand, take as is
3 source operand, take negative of absolute value
4 destination operand, shift right
5 destination operand, shift left
6 destination operand, shift right +10 places
7 destination operand, shift left +10 places
8 destination operand, shift right +20 places
9 destination operand, shift left +20 places

This allows right or left shifts of up to 29 places to be specified for destination operands despite the fact that the shift field in the instruction is only one digit long.

When the b field for an operand is 0, that means the operand is to be ignored.

The SSEC executed instructions in pairs; they belonged to either instruction stream S1 or S2. In the second instruction of a pair, there was a case where the first address field in the instruction would indicate a destination operand instead of a source operand; while the s field within that address field could still only be from 0 to 3, this was overridden by the one instruction opcode that turned the first operand into a destination.

The 150 locations in relay storage were assigned addresses from 010 to 159, where the last digit indicates one of ten banks of locations, and the first two digits indicate the location within that bank. Plugboards could be used to make some locations in relay memory behave in an unusual way, for example, allowing a number to be built up from digits of two other numbers without using shifting and adding. The ten reading stations for each of the three tape storage units normally had the addresses 503 to 522 for the first unit, 533 to 552 for the second, and 563 to 582 for the third; subtracting 100 from the address gave an alternate address that would read the number at the same read head, but not advance the tape there.

The meanings of the two-digit address codes in the S1 and S2 sequence fields weren't fixed, but were assigned from a plugboard, so it was possible, for example, to assign ten addresses to ten consecutive locations in relay storage, with a program placed there using the S1 and S2 fields to ensure stepping before returning to a tape reader.

The conditional test instructions that the machine had normally allowed operation to continue, or to halt operation. Apparently, plugboard control was used so that when instructions were obtained from a tape loop, control would return to the parent source of program steps without manual intervention. Also, note that the two-digit sequence field indicated where the next instruction from the same sequence would be taken; that is, an S1 instruction is followed by an S2 instruction; the sequence field of an S1 instruction gives the source for the next S1 instruction, not the immediately following S2 instruction, and similarly the sequence field of an S2 instruction gives the source for the next S2 instruction, not the immediately following S1 instruction.

It does seem, though, from the hints in the description that even if the machine did not attempt to be a full-fledged stored-program computer, time on it being too scarce to, for example, write a compiler for it, it could well be that instructions were generated on the main storage units, and executed from there, in order to permit self-modifying code to make up for the absence of index registers. The index register, as the "B-line", had yet to be invented at the time of the SSEC, and when neither index registers nor indirect addressing is available, the remaining way to reference an element of an array is to add the desired index to the address field of the instruction to be used. So there is reason to suspect that at least this aspect of the behavior of a stored-program computer was indeed present in the SSEC.

The fact that it would normally use up large quantities of paper tape in order to perform a calculation, with working-storage units in which numbers could only be read ten times before being lost, made it an unusual machine, a large-scale machine that embodied the transition between the electromechanical and the electronic. As in many later computers, including those in use today, the design attempted to make the best possible use of a small number of expensive high-speed components, and a larger number of less-expensive lower-speed components, whether as a memory hierarchy (hard disk, DRAM, cache) or in logic (regular CMOS, domino logic). Also, it received the attention of the public and the mass media, contributing to the image of computers as large and impressive machines.

[Up] [Previous] [Next] [Next Section]