The formats of the basic 32-bit instructions for this architecture are shown in the two diagrams below:
First, the instructions that are 32 bits in length which can never affect the condition code bits, as they perform functions such as load and store, or jump, are shown.
The 32-bit form of basic load and store instructions is shown in lines 1 through 8.
For a memory-reference instruction, the five-bit destination register field specifies one of 32 registers, either the general-purpose registers for integer instructions, or the floating-point registers for floating-point instructions.
The index register field contains a number from 0 to 7, if it contains 0, the instruction is not indexed; if it contains any other value, that value indicates which general register is to be used as the index register for that instruction.
Lines 1 through 8 show the eight possible formats for 32-bit memory-reference instructions.
In line 1, a three-bit field indicates the base register. It may contain any value from 1 to 7, which indicates that a general register from 25 to 31 respectively is used as the base register.
Line 2 of the original diagram shows the second possibility: a 15-bit displacement is included in the instruction, and general register 16 contains the starting point of the 32,768-byte area of memory to which the values of this displacement may refer.
Line 3 of the original diagram shows the third possibility. Here, the displacement is 12 bits long, and there is a three-bit ssB field (short source base) adjacent to it.
If that field contains a number from 1 to 7, it indicates that a register from 17 to 23, respectively, is used as a base register, the contents of which point to a 4,096-byte area in memory.
If that field contains a 0, then one of the possibilities shown in lines 4 and 5 of the diagram apply.
Line 4 of the original diagram shows this possibility: if the ssB field, containing a 0, is followed by 00, then program-relative addressing is indicated.
The instruction now contains an 10-bit displacement, which is in units of bytes, but now it is a signed two's complement value from -512 to 511, relative to the position immediately after the end of the instruction. One particularly important application of this addressing mode is at the beginning of a main program or a subroutine, where a Jump to Subroutine instruction having the following instruction as its destination can be used to initialize a base register by means of which adresses referring to the program code can be constructed.
Lines 5 and 6 of the diagram are chiefly concerned with the register indirect addressing modes.
In line 5, we see where the ssB field, containing zero, is followed by 01, and the following mode field contains a value from 0 to 5, indicating an addressing mode used with one of the registers in the extended register bank.
These modes are:
000 Register Indirect 010 Register Indirect with Scaled Auto-Increment 011 Register Indirect with Scaled Auto-Decrement
In line 6, the ssB field again contains zero, and is followed by 0111 and then
a mode field. This field applies either to a register from the normal bank of
32 integer registers, or, in one case, the field normally specifying a register instead
contains a pseudo-immediate pointer. The modes are:
000 Register Indirect 010 Register Indirect with Scaled Auto-Increment 011 Register Indirect with Scaled Auto-Decrement 111 Absolute
In the absolute addressing mode, which may be indexed, the source register field instead contains a five-bit pseudo-immediate pointer which points to a 64-bit pseudo-immediate used as the address of the instruction.
For all load operations, auto-increment and auto-decrement are performed after the load operation; for all store operations, auto-increment and auto-decrement are performed before the store operation. In this way, it is possible for stacks to grow either up or down in memory, whereas, if whether an auto-increment or auto-decrement were performed had determined the ordering of operations, a specific direction of stack growth would be imposed.
Lines 7 and 8 of the diagram show the formats for two other addressing modes.
If the ssB field,
containing a 0, is followed by 100, then it indicates Array Mode addressing.
Here, the contents of register 16 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit pointer to an array.
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Unless the displacement begins with
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If indexing is present in the instruction, the contents of the selected register are added to that pointer in order to address an element of that array. Thus, Array Mode provides post-indexed indirect addressing in order to conveniently allow a program to refer to up to 512 arrays which are larger than 65,536 bytes in size without having to reload base registers in order to access them.
If the ssB field,
containing a 0, is followed by 101, then Address Table addressing is indicated.
Here, the contents of register 16 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit constant containing the effective address of the instruction.
If indexing is present in the instruction, the contents of the selected register are added to the initial effective address formed by adding the contents of register 17 to the displacement, so as to change which 64-bit constant is taken as the effective address.
Thus, Array Mode addressing provides pre-indexed indirection, and Address Table addressing provides post-indexed indirection. Array Mode addressing is useful for accesing data in multiple large arrays without reloading base registers, and Address Table addressing is useful for such things as multi-way jump tables.
If the ssB field, containing a 0, is followed by 110, then Array Mode with
Auto-Increment addressing is indicated. The displacement is in units of 64 bits, and
the contents of integer register 16 are added
to the displacement after scaling to find the address to be used; this address may be indexed to form
the effective address, and, in addition, after the memory location at the effective address so calculated
is accessed, the index register is then incremented by the size of the operands of the instruction;
incremented by one if the instruction acts on bytes, having eight added to it if the instruction acts
on double-precision floating-point numbers, and so on. This includes adding six in the case of medium
floating-point numbers.
If the ssB field, containing a 0, is followed by 111, then Array Mode with
Flexible Auto-Increment
addressing is indicated. Here, if the instruction is indexed, the index register must be one of
registers 2, 4, or 6, and the amount by which it is incremented after memory access is found in the
following register.
Line 9 of the diagram shows the format of the Load Address instruction. It has all the same addressing modes as the regular memory-reference load-store instructions shown in lines 1 through 8 of the diagram, but it may only have register 0 or 1 as its destination register.
Lines 11, 12, and 13 of the diagram show the formats of the multiple-register load and store instructions:
1506xx xxxxx LM Load Multiple 1507xx xxxxx STM Store Multiple 1546xx xxx0x LMF Load Multiple Floating 1547xx xxx0x STMF Store Multiple Floating 1546xx xxx1x LMSV Load Multiple Short Vector 1547xx xxx1x STMSV Store Multiple Short Vector
Note that these instructions, in particular the ones for the floating-point registers, load and store their contents in raw internal form. Because of the complexities of the IEEE 754 format for floating-point numbers, they are converted to an internal form when loaded into the floating-point registers, and converted back to the standard form when stored from those registers, to allow register-to-register arithmetic to proceed more quickly.
As these instructions, with both a low and high register specified, require a considerable amount of opcode space, they have been restricted to aligned operands.
Lines 20, 21, and 22 show the form of the Supplemental Load and Store operations. These instructions perform load and store operations from memory for operands of additional specialized types which are supported by some of the operate instructions with longer opcodes.
In order to allow these instructions to fit in the available opcode space, they have a number of limitations.
The Subroutine Jump instruction, depicted in line 23 of the diagram, has some important properties in this architecture that should be noted. Normally, the address of the location immediately following the instruction is stored in the return register field. But if the Subroutine Jump instruction is not in the last instruction slot of the current instruction block, but is still the last executable instruction in the block, the remaining part of the block being reserved, then the beginning of the next instruction block is used as the return address.
This avoids the need to fetch the next instruction block in order to scan it for its header, since a branch to the beginning of a block is always treated as a branch to the first executable instruction in a block.
Also, when a Subroutine Jump instruction is within a block where the starting positions of instructions are indicated for code with variable-length instructions, the actual position of the next executable instruction within the block as so indicated is used as the return address.
The diagram below shows the format for 32-bit instructions which perform arithmetic operations, and which may affect the condition codes:
A three-address register-to-register operate instruction is shown in lines 1 through 3; either one of the source and operand registers may be replaced with pointers to pseudo-immediate operands. As the result of the instruction would be a constant if both of those operands were so replaced, this combination is illegal, and the bit pattern it would have is reserved for future expansion of the instruction set.
Two-address register-to-register operate instructions are shown in lines 4 and 5. These have a considerably larger space available for the opcode field, and, thus, are not restricted to the basic arithmetic operations provided for three operands.
Line 9 shows a two-operand register-to-register operate instruction that can use any of eight possible sets of condition codes, if the C bit is set, instead of just the normal set of condition codes. Like the flag bits used with instruction predicatiion, alternate sets of condition codes are a way to allow conditional branches to be delayed so as to reduce the need for branch prediction.
Line 10 shows register-to-register operate instructions that involve extended register banks, both integer and floating, with 128 registers instead of 32 registers. Larger register banks permit more operations to be performed before there is a need to re-use a register from which the result has been stored, reducing the occurence of hazards in pipelined code.
The mixed register two-address instructions in line 11 allow the large register banks to interact with the normal register banks.
Line 11 shows the Alternate Condition Code operate instructions; these instructions, instead of setting the normal condition codes, set one of eight alternative sets of condition codes. This helps to delay branches for better pipelined execution. Due to limitations of opcode space, these instructions may only use the first eight registers in each register bank as destination registers; a version without this restriction is in a set of alternative instructions.
Line 12 shows the halfword immediate instructions. Since a store immediate instruction does not make sennse, that opcode is used for the instructions in Line 11 instead.
In blocks with a type I, type II, or type VII header, as a consequece of headers only appearing at the beginning of the instruction block, some additional opcode space is also available for additional 32-bit instructions, the format of which is shown here:
Here we see memory to register operate instructions. In order to fit them in to the available opcode space, multiple restrictions have had to have been imposed on this group of instructions:
Even with these restrictions, the ability to combine a fetch of data from memory with an operation should prove useful.
In blocks with a Type III or Type VIII header, these instructions are superseded by the 35-bit instructions, to be described later, and so the instructions in this portion of the opcode range are reserved for future expansion.
As well, a full alternate set of 32-bit instructions is normally available with
the Type II, Type III and Type VIII headers. These instructions, the ones indicated
in the Type II header by bits set to 1 in the alternate
field (subject to the effects of the D bit if set), and
in the Type III and Type VIII by following the prefix
bits 010 with the prefix bits 111, have the formats shown
below:
A set of supplemental load/store instructions for additional data types is now available with the same full set of addressing modes as the regular load/store memory-reference instructions. Also, multiple-register load and store instructions are provided; like those in the basic instruction set, they are restricted to aligned operands, but now they have 16-bit displacements. As well, three-operand register-to-register operate instructions with longer opcodes are provided.
In line 15, the Subroutine Jump with Offset instruction is shown. This operates like a normal subroutine jump instruction, except that the contents of the three-bit offset field, shifted one place to the left, are added to the return address. This permits more efficient handling of a subroutine call as the last instruction of a block.
It is intended that the value in the offset field be set so that the return address points to an actual executable instruction. Normally, if it fails to do so, an error may result.
However, while this instruction does not perform the special processing that the regular subroutine jump instruction does in order to modify the return address, if the effective return address is the beginning of the next instruction block, normal processing will take place, since any branch to the beginning of an instruction block leads to execution of the first executable instruction in the block; this processing is part of the handling of all branches, and does not occur within the subroutine jump instruction itself, but in the jump instruction performing the return.
Note, incidentally, this is the one exception to the rule that a branch to a location which is indicated by the block header not to be the start of an executable instruction will cause an error. And when a block does not have a header (and also when there is a header which is not one of those indicating code composed of variable-length instructions), all addresses aligned to 16 bits but not aligned to 32 bits within that block are invalid as branch targets, unless they are within an instruction slot containing paired short instructions, in which case the branch is to the second of the two paired instructions.
Also, note that in the case of the Type VIII header, if the R
bit is set, then these instructions are not available, as the prefix bits
111 are no longer available to indicate an additional bit or option
for 32-bit instructions.
In blocks with a Type V header, a different type of alternate instruction set is made available.
The alternate instruction set previously described is indicated for individual instruction slots, and therefore can supply additional instructions which supplement the basic instruction set.
This alternate instruction set, on the other hand, is selected for the entire block, and must therefore be at least nearly complete in itself. Its purpose is to allow a format for paired short instructions which makes use of fully half of the opcode space available for 32-bit instructions.
In this alternate instruction format, therefore, opcode space is saved by limiting the load/store memory reference instructions to aligned operands, as shown below:
Their opcodes are:
000xxx xxxxxx LB Load Byte 004xxx xxxxxx STB Store Byte 010xxx xxxxxx ULB Unsigned Load Byte 014xxx xxxxxx IB Insert Byte 020xxx xxxxx0 LB Load Halfword 024xxx xxxxx0 STB Store Halfword 030xxx xxxxx0 ULB Unsigned Load Halfword 034xxx xxxxx0 IB Insert Halfword 020xxx xxxxx1 LB Load 024xxx xxxxx1 STB Store 030xxx xxxxx1 ULB Unsigned Load 034xxx xxxxx1 IB Insert 020xxx xxxxx3 LB Load Long 024xxx xxxxx3 STB Store Long 040xxx xxxxx0 LM Load Medium 044xxx xxxxx0 STM Store Medium 040xxx xxxxx1 LF Load Floating 044xxx xxxxx1 STF Store Floating 040xxx xxxxx3 LD Load Double 044xxx xxxxx3 STD Store Double 040xxx xxxx07 LQ Load Quad 044xxx xxxx07 STQ Store Quad
Other required instructions are shown below:
In instruction blocks with Type III and Type VIII headers, memory-reference operate instructions are made available. These instructions are 35 bits long, and have the following format:
Also, the Type VIII header contains an R bit. If that bit is set, the 17-bit short instructions are replaced by 18-bit short instructions, which may set the condition codes, and the 35-bit instructions are replaced by 33-bit instructions which may not set the condition codes. The format of the 33-bit instructions is shown below:
As the format of the header necessitated shortening these instructions by two bits, in addition to removing the C bit from the instructions, they had to be limited to operating on only the first 16 registers in either register set as destination registers.
Also in the Type VIII header, when the R bit is not set, but the bit preceding it is set, 34-bit instructions are available, which have the following format:
These also do not set the condition code bits, but at least they use all 32 registers as possible destination registers.
In this case, the header also contains a U bit; if that bit is set, instead of being operate instructions, the 34-bit instructions are load/store memory-reference instructions, but ones that can use any register except register zero as an index register. The format of the 34-bit instructions in this case is:
