Welcome to the home page of the Concertina II computer architecture.
The original Concertina computer architecture was originally intended as a simple example of a conventional old-style CISC architecture, to help explain how computers work. It was expanded over time to include many features from a wide selection of historical computer architectures, to explain those as well.
Concertina II was intended as an ISA that could conceivably be of practical use in an actual implementation. However, I cannot make ambitious claims for it, as my experience in this area is quite limited. This architecture went through quite a number of drafts before I felt that I had struck an acceptable balance between the various factors that had to be compromised to provide the architecture with the capabilities I sought.
However, I believe that the current version of the ISA is a sound basis on which to proceed, and I only expect to be changing it with minor tweaks as I continue to flesh out the architecture and describe its features.
Once I have it completed, it may serve as an alternative to RISC-V, even though the designer of that architecture is far more knowledgeable and experienced than I am. This is because I feel it may at least suit some people's tastes more than RISC-V does.
What is the Concertina II ISA, and what choices were made in its design?
The Concertina II design is still unfinished; many parts of it are yet to be described, and, although I do not intend to tear it up and start afresh, as I no longer feel I will be able to do better, it is still subject to minor tweaks.
It will be freely available to all to implement without restrictions once completed, subject to export controls on computer technology.
The basic Concertina II instruction set is largely patterned after today's most popular type of ISA (instruction set architecture) design, RISC (reduced instruction set computing), but it does not qualify as a genuine RISC design by any reasonable contemporary definition of RISC, even the least puristic.
The basic instruction set consists of 32-bit instructions, but also adds the ability to use a pair of 16-bit instructions at any point in the sequence of instructions in place of a 32-bit instruction.
This allows increasing code density by using smaller instructions for many operations, without losing the simplicity of fetching and decoding instructions gained by having all instructions of the same length.
As in many RISC designs, there are two main register files, one for integer values (with registers that are 64 bits wide) and one for floating-point values (with registers that are 128 bits wide), each of which contains 32 registers.
Also, the memory-reference instructions are of the load-store variety, following standard RISC practice.
The following extensions to the RISC model are included in the most basic portion of the instruction set:
It is precisely because base-index addressing is provided by restricting potential index registers to registers 1-7, and potential base registers to groups of 7 (which group depends on the displacement length) that this design does not qualify as RISC, and instead could be called CISC in RISC clothing.
Typically, RISC architectures normally only allow two registers to be indicated in a memory-reference instruction. One is the destination register of the instruction, and the other one is the one the contents of which are added to the displacement to form the effective address, Since a base register is needed for any memory access when the displacement is not large enough to indicate any location in the available memory, this means that the advantage of having an index register isn't available, and array access require additional explicit arithmetic instructions to compute addresses.
Thus, since the use of arrays is a very common operation, full base-index addressing was considered a very important feature to add.
In order to make it possible to provide this feature, the integer registers were split up into groups of eight so that the index register and base register fields could be only three bits long instead of five bits long, thus allowing both to fit in an instruction.
Normally, if one allocates a block of memory containing 65,536 bytes, using a base register to point to that block, it is not useful to have addressing modes that can only access the first 4,096 bytes of that block. Therefore, separate groups of registers are used as the possible base registers for different sizes of displacement values.
Only one register serves as the implicit base register for 15-bit displacements; this is done to allow one larger block of memory to be used in conjunction with those accessed with 12-bit displacements. This permits more compact memory-reference instructions, and is inspired by the System/360 Model 20 computer.
The above summarizes how the basic instruction set of this computer was designed to take the basic RISC design, and offer important extensions to it, while still having instructions that fit in 32 bits.
But a number of other extensions are also offered. These require going beyond the somewhat RISC-like model of the basic instruction set, and instead recognizing that this architecture also has VLIW (Very Long Instruction Word) characteristics.
Instructions are grouped in blocks of 256 bits, each of which contains eight 32-bit instruction slots. If feasible, an implementation aiming for maximum performance should have at least a 256-bit data bus to main memory, permitting a block of instructions to be fetched at once.
A small portion of the opcode space for instructions is dedicated to codes which represent headers instead of instructions. A block may begin with a header, and if it does, an additional header may follow it. A header may be 32, 48, or 64 bits long. 48-bit long headers are possible because some headers indicate that the instruction set to be used in the current block will not be the basic one composed only of 32-bit instructions, but instead one containing variable-length instructions, with the length of each instruction being a multiple of 16 bits.
Headers, if any, are processed before the instructions in a block are decoded.
After the headers are processed, or after it is determined that the block does not begin with a header, the computer has the information required to decode all the instructions in the block in parallel.
One of the most important features that having headers provides, which is still considered part of the basic instruction set of the Concertina II architecture, is pseudo-immediate values.
Some register-to-register instructions may have a source register specification replaced by a five-bit byte pointer to an address within the current instruction block, which points to an operand for that instruction.
This capability is supported by headers which contain a three bit decode field, which indicates that some of the eight 32-bit instruction slots in the current block are to be ignored during instruction decoding, and skipped over in execution, so that pseudo-immediate values can be placed in them.
What are pseudo-immediate values, and why are they included in this ISA? Essentially, they are inspired by the Heads and Tails design of Heidi Pan. As Mitch Alsup has reminded us all in the design of his "My 66000" ISA, immediate mode instructions have the advantage that a constant value can be used in a calculation without requiring an additional fetch of data, with all the delays and overhead of memory accesses in modern architectures, where DRAM is slow compared to processor logic.
This is because the immediate value is part of the instruction itself, and thus has already been fetched as part of the instruction stream.
But since data items come in several widths, comprehensive support of immediate values means that instructions must come in many different lengths, and I felt this would complicate their decoding to an unacceptable extent.
With pseudo-immediate values, the length of the instruction doesn't have to be changed. A pointer to the value only takes up the same space as a register specification.
But if the value is fetched from a location indicated by a pointer, it isn't an immediate value any more. Hence the term "pseudo-immediate" - given that instructions are fetched from memory in 256-bit blocks, and the data to which the pointer refers is within the same block as the instruction itself, even though the values are not actually immediate values, they still offer the same basic advantage as immediate values. (To some extent, of course, this depends on how the implementation handles the instruction stream. Specifically, to gain the full advantages of this, the entire block needs to be buffered within the processor during instruction decoding.)
In addition to pseudo-immediate values, headers allow two basic sets of features to be added to the ISA that go beyond the RISC model.
Thus, while the architecture initially has the appearance of a conventional RISC architecture, it is intended to combine the basic features and advantages of RISC, CISC, and VLIW architectures.
Note, however, that by VLIW, I mean modern VLIW architectures, such as the Itanium or, even more particularly, the Texas Instruments TMS320C6000 chip, and not the type of classic VLIW architecture the term was originally concieved of as referring to, such as that of the Control Data Cyber 200 computer.
Given that both the Itanium and the i860 were failures in the marketplace, despite being backed by the might of Intel, it is understandable that some might doubt my sanity in proposing a VLIW design in this day and age.
However, instead of including a break bit in every instruction, the break bits are in an optional header at the beginning of a 256-bit block of instructions. Implementations don't need to be designed around VLIW operation, but they can be, if they are aimed at a niche where a VLIW design is appropriate.
There are 32 integer general registers and 32 floating-point registers, and those instructions that perform arithmetic or logical operations include a bit for enabling changes to the condition codes as a result of those instructions. These are characteristics found in RISC architectures.
Having register banks of 32 registers allows different calculations to be intertwined in the code, and being able to control if instructions affect the condition codes allows more intervening instructions between an instruction that sets the condition codes and a branch instruction that makes use of those results. Both of these things allowed code to be designed to offer some of the same benefits as are obtained from out-of-order execution, without the hardware overhead. However, at the microprocessor clock rates in use today, these measures normally are not enough to be effective: however, if code written this way is combined with simultaneous multi-threading (SMT), then there is still the potential for competing with out-of-order execution.
Also, the architecture provides extended register banks of 128 integer registers, 64 bits in width, and 128 floating-point registers, 128 bits in width, which will also promote efficient VLIW operation.
Instructions are organized into 256-bit blocks which contain eight 32-bit instruction slots.
These blocks are always aligned on the boundaries of aligned 32-byte areas in memory, so an instruction slot that may contain the initial header of a block must have an address the last five bits of which are zero.
When a block header makes provision for instructions longer than 32 bits, it is possible that these instructions may cross block boundaries, depending on the rules applicable to the particular block header format in use. Specifically: the Type I and Type VIII headers do not allow instructions to cross block boundaries at either end, either in to such a block, or out from such a block; the Type II, Type VI, and Type VII block headers do allow instructions to cross block boundaries; as these block headers support related instruction sets, it is also possible for instructions to cross from a block beginning with one of these three types of header into an instruction block beginning with this kind of header. In this case, the instruction set available is determined by the nature of the block in which the instruction begins; that it may continue into a block in which an instruction of its type cannot be indicated is not to interfere with its successful execution in a conformant implementation.
The instruction set is organized so that the computer is able to fetch a 256-bit block of instructions, and, after processing any block header within the block, to determine what, if any, special processing is required, immediately begin decoding each 32-bit instruction slot independently of the others in the block.
There are a few different types of block header, which are shown in the diagram below.
Eight types of header are illustrated in this diagram. These are those that are required to provide the functionality that will be described here.
The first type of header allows for instructions of different lengths to be
mixed. Each 1 bit in the instruction start field
indicates the beginning of an instruction. This instruction will normally be
32 bits long, or possibly longer. The only exception is where a 1
bit is followed either by another 1 bit, or the end of the
instruction start field, in which case it indicates the
start of a 16-bit short instruction.
An instruction block which starts with a Type I header is subject to
the following two restrictions: it must contain at least two executable instructions,
and the first two instructions in the block must be contiguous. Because of these
two restrictions, combined with the fact that no instructions exist that are longer
than 96 bits, a valid block with a Type I header may not begin with 11000000,
which distinguishes the Type I header from the Type II and Type III headers described
below.
In addition, in 64-bit mode, the additional restriction is imposed that the first executable instruction in a block starting with a Type I header may not be a 16-bit short instruction.
It was considered acceptable to impose this restriction because the 16-bit short instruction format is quite limited, and thus the Type I header is intended to be primarily used for allowing 32-bit instructions to be mixed with instructions longer than 32 bits with the lowest possible overhead. If short instructions are important, the Type II header, which allows 17-bit short instructions, is usually preferred, and this type of header is precisely the one imposing this restriction makes available.
The second type of header allows for instructions of different lengths to be freely mixed. This is achieved by having fourteen two-bit prefix fields in the header, each of which corresponds, in order, to the remaining 16-bit halves of the seven remaining instruction slots in the current instruction block.
These fields each indicate what is contained in the corresponding 16-bit area of the instruction block, and are interpreted as follows:
00 A 17-bit instruction starting with 0 01 A 17-bit instruction starting with 1 10 The start of an instruction 32 bits in length or longer 11 Not the start of an instruction
Note that the prefix value of 10 must always be followed by the prefix value of 11. An invalid combination where this is not the case is used to distinguish the remaining types of header, so as to avoid the need for additional opcode space for those headers.
The third type of header also functions as a two-operand register-to-register operate instruction, as well as a header which, with its decode field, specifies the number of 32-bit instruction slots at the end of the block which are not decoded as instructions, but are instead reserved for other purposes, such as the data values for pseudo-immediates.
The decode field is used to indicate the number of 32-bit instruction
slots that are reserved for data other than instructions, such as pseudo-immediate values,
for which no attempt is to be made to decode them as instructions. A value of 000
in the decode field indicates that all the remaining instruction slots are
to be decoded as instructions; a value of 001 indicates the last instruction
slot is to be reserved, and not decoded, and so on.
An immediate value in an instruction allows it to perform an arithmetic operation involving a constant without having to perform a fetch of data from memory in addition to the fetching from memory already performed as part of reading in the instruction stream.
An important design goal of the Concertina II architecture has been to drastically simplify the decoding of instructions; once a 256-bit instruction block has been checked for a header, and that header, if present, has been processed, all the instructions in the block can be decoded in parallel independently. The varying lengths of different data types mean that including a wide selection of instructions with immediate values would conflict with this.
A pseudo-immediate is addressed by a pointer in the instruction, which seems to be the same thing as a memory-to-register instruction making use of a constant value stored somewhere else. However, the pointer is a short-range one, which only points to a location within the same 256-bit instruction block as the current instruction is contained in.
Therefore, although it involdes a pointer reference, and thus is not "really" an immediate, hence the name "pseudo-immediate", it provides the same advantage of the constant argument having been fetched as part of the instruction stream!
This fourth type of header reserves space for these constants which therefore won't be decoded erroneously as instructions, and because the header is also an instruction, it lets these three bits of information be provided without the overhead of using a full 32-bit instruction slot for a header and nothing else.
Also, like the fifth and sixth types of header, this header contains a A bit, so that the alternate version of the instruction set which it indicates may be accessed with low overhead.
The fourth type of header provides a three-bit prefix field for each remaining 16-bit area in the current instruction block, so as to allow both 17-bit short instructions and 35-bit memory-reference operate instructions without restriction.
The bits in a prefix field normally are interpreted as follows:
000 A 17-bit instruction starting with 0 001 A 17-bit instruction starting with 1 010 The start of an instruction 32 bits in length or longer 011 Not the start of an instruction 100 The start of a 35-bit instruction starting with 00 101 The start of a 35-bit instruction starting with 01 110 The start of a 35-bit instruction starting with 10 111 The second half of a 35-bit instruction the third bit of which is a 1
The 35-bit memory-to-register operate instructions are as illustrated on the next page. When the
third bit of a 35-bit instruction is a zero, its second half is indicated in the same normal way
as used for the second half of a 32-bit instruction, with 011 in the prefix
field. The relationship between the prefix bits, the contents of the 16 bit halves of instruction
slots to which they correspond, and the canonical form of a 35-bit instruction is shown in the
diagram below:
The prefix bits are shown raised immediately before the contents of the 16-bit extents in the diagram, although in the actual instruction block in memory, they are separated, as the prefix bits are in the header, and the 16-bit extents are contiguous with each other afterwards.
As well, it is possible to follow the prefix 010 by the prefix 111
instead of by the prefix 011. This indicates an alternate set of 32-bit instructions.
The fifth type of header provides supplementary information which allows the computer to provide VLIW functionality.
The primary feature of this type of header is to provide for VLIW features which can be used to accelerate the speed of instruction execution, particularly on lightweight implementations of the architecture which lack out-of-order execution.
There are seven bits marked B, for break; they correspond to the seven remaining 32-bit instruction slots in the block, and if a bit marked B is set, this indicates that the instruction in its corresponding instruction slot may not be executed in parallel with the instructions that precede it.
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Important note: it is intended that this ISA may be implemented in a number of ways. Specifically, in relation to the VLIW feature of the break bit, these three classes of implementations are possible:
In consequence, any programs which would produce a different result on the first two types of implementation listed above are to be considered to be invalid programs which have been written incorrectly. Thus, the architecture specification requires implementations to execute code which does not contain any explicit indications of parallel execution with sequential consistency. When code does contain such indications, implementations may follow those indications, or they may execute the code sequentially, even if different results are produced in the two cases; it is the programmer's responsibility, if consistent model-independent execution of programs is desired, only to indicate parallelism where it does not lead to results different from those of completely sequential code. |
In this header format, there is also a four-bit flag field. This indicates which of the sixteen flag bits may be used for predicating instructions in this block. A seven-bit predicated field indicates which instruction slots contain an instruction the execution of which is conditional, based on that flag bit. There is also a bit marked S, for sense; if that bit is zero, a predicated instruction will execute if and only if the selected flag bit is set (equal to 1); if it is one, the predicated instruction will instead execute if and only if the selected flag bit is cleared (equal to 0).
This header also has a decode field.
In addition, this type of header includes a A bit. If this bit is set, the instructions in the block belong to a modified version of the instruction set, in which paired short instructions are guaranteed to both be able to execute in parallel. As this type of paired short instruction requires more opcode space than the regular 15-bit instructions, the standard memory-reference instructions are also modified by being restricted to aligned operands, so as to make more opcode space available.
The sixth type of header is used to provide a security feature for the architecture.
In the page table, a region of memory which will be used for executable code may be designated as having branch control. In that case, branches to instructions within that region of memory will only be permissible if the instructions are within an instruction block beginning with a header of the fifth or eighth type, and only under the conditions specified by that header.
The decode field has its usual meaning in this header.
The type field indicates what type of branches are permitted to the potential branch targets indicated by this header:
00 This indicates an entry point, with branches to the branch target being permitted from anywhere. 10 This indicates a local branch target. Only branches in the same page of storage are permitted. 11 This indicates a single-source branch target. Only branches from a specific address are permitted.
In the case of a type field containing 11, the instruction
indicated as a branch target is to be immediately followed by a 64-bit absolute address indicating
the location of the branch instruction that is permitted to branch to the instruction.
By an absolute address, an address relative to the address space of the current program is meant, so it is not required to add the contents of any base register to the address. But it is still not a physical hardware address, since offsets due to the page table mechanism and similar functionality transparent to the programmer are still applied.
The bits of the target field each correspond, in order, to one of the
remaining 32-bit instruction slots in the current instruction block, and if a bit is
1, it indicates that the instruction in the corresponding position may be
the subject of a branch instruction, subject to the criterion indicated by the type
field.
Like the third and fifth types of header, this header also contains a A bit, so that the alternate set of 32-bit instructions which it indicates may be available within all blocks with a header that do not contain variable-length instructions.
The seventh type of header allows code with variable-length instructions, in the same fashion as the Type II header. As well, it also includes some additional bits which affect how instructions are interpreted.
This type of header contains a bit marked C. This indicates that, for all operate instructions in the block of a type such that the opcode field may indicate floating-point instructions with the default Standard format for floating-point numbers, but which cannot, perhaps because of not being long enough, indicate floating-point instructions in the Compatible floating-point format, those instructions are interpreted as being for the Compatible floating-point format instead.
This unusual option is provided for this particular block format as it is focused on providing instructions which perform the same operations of those of a particular popular mainframe architecture.
There is also a bit marked T, which causes floating-point operations in the Compatible floating-point type performed by instructions within the block with this header, instead of having normal rounding behavior (which is to be rounded to the value closest to the exact result, as specified in IEEE 754, for addition, subtraction, and multiplication, and to a result within 1/64 of the units in the last place of the exact result for division, just as in the case of the Standard floating-point type), to be truncated, for further compatibility. This bit does not affect any instructions in which the rounding type is explicitly indicated in the instruction.
In addition, this header type contains a bit marked E. When this bit is set, for the instructions starting in the block, the first sixteen floating-point registers, as seen by the program, are changed from 128-bit registers to 64-bit registers, and they are placed in pairs in the first eight actual 128-bit floating-point registers of the machine. Registers 16 through 31 are not changed.
This affects instructions operating on both the Standard and the Compatible floating-point formats.
The purpose of this is to enable code with this header type to interface with code running in emulation mode for one particular computer architecture.
The locations of the 64-bit registers within the 128-bit registers are shown in the table below:
128-bit 64-bit register registers 0 0,2 1 4,6 2 8,10 3 12,14 4 1,3 5 5,7 6 9,11 7 13,15
This arrangement stems from the historical characteristics of the architecture being emulated; originally, it only had four floating-point registers, and they were numbered 0, 2, 4, and 6, and so when a register pair was needed, only even-numbered registers were available out of which to build it.
A pictorial representation of this arrangement is shown below:
The rightmost portion of the image is after Figure 2-2 on page 2-5 of the Ninth Edition of Enterprise Systems Architecture/390 Principles of Operation, publication SA22-7201-08, by IBM.
A block header with this bit set also modifies the behavior of floating-point instructions involving the Standard floating-point type in another important way. Since the first sixteen registers are now only 64 bits long, floating point values in these registers will be in the same form as they are kept in main memory, and will not be converted to internal form on being loaded, and from internal form on being stored.
The conversion will remain in place for registers 16 through 31, since the purpose of this block format is to facilitate communication between programs running in emulation mode and ordinary programs. Thus, instructions operating on 128-bit floats in the Standard floating-point type will continue to use the internal form of floats without a hidden first bit, rather than the IEEE 754 standard format for 128-bit floats.
Alternatively, instead of providing the T, C, and E bits, this type of header may contain a length field.
This field is used for an optional advanced feature of the architecture, which allows it to utilize areas of memory that are organized so as to appear as if the memory has a different width in bits; instead of being divided into units of 8, 16, 32, and 64 bits, and so on, division into units of 9, 18, 36, and 72 bits, or 6, 12, 24, 48, and 96 bits, or even 15, 30, and 60 bits can be selected, if hardware support is provided.
This would be achieved by techniques such as three-channel memory which are compatible with operation with the normal power-of-two widths of memory continuing to be the default mode of operation.
The eighth type of header combines the additional options provided by the eighth type of header with the extended instruction set provided by the fourth type of header.
In addition, it includes a R bit. If that bit is set, then the alternate set of 32-bit instructions is not available, and the interpretation of the prefix field is changed to the following:
000 The start of a 33-bit instruction starting with 0 001 The start of a 33-bit instruction starting with 1 010 The start of an instruction 32 bits in length or longer 011 Not the start of an instruction 100 An 18-bit instruction starting with 00 101 An 18-bit instruction starting with 01 110 An 18-bit instruction starting with 10 111 An 18-bit instruction starting with 11
The purpose of the R bit is to switch to a situation where the short instructions, increased in length to 18 bits, now include a condition bit, so that they may optionally affect the condition codes, while the memory-reference operate instructions, decreased in length to 33 bits, do not have the ability to affect the condition codes.
In code running in 32-bit mode, the Type II and Type III headers take on a different form, since Unsigned Load and Insert instructions are no longer used for 32-bit values, as the integer registers are now 32 bits wide instead of 64 bits wide. Instructions doing arithmetic on 64-bit Long integer values still exist in that mode, but they now operate on pairs of registers, the first of which must be even-numbered.
The format of the modified form of these headers is shown below:
This allows the restriction on the Type I header that the first instruction in the block cannot be a 16-bit instruction to be lifted.
The basic complement of registers included with this architecture is as follows:
There are 32 integer registers, each of which is 64 bits in length, numbered from 0 to 31.
Registers 1 through 7 may be used as index registers.
Registers 25 through 31 may be used as base registers, each of which points to an area of 65,536 bytes in length.
Register 24 serves as a base register which points to an area 32,768 bytes in length.
Registers 17 through 23 may be used as base registers, each of which points to an area of 4,096 bytes in length.
At least part of the area of 3,072 bytes in length pointed to by register 16 will normally be used to contain up to 384 pointers, each 64 bits in length, for use in either Array Mode addressing or Address Table addressing.
Registers 9 through 15 may be used as base registers, each of which points to an area of 1,048,576 bytes in length. This addressing format is used for 48-bit extended memory-reference instructions.
Register 8 serves as a pointer to a table of pseudo-operations, if this feature is used.
There are 32 floating-point registers, each of which is 128 bits in length, numbered from 0 to 31.
Floating point numbers in IEEE 754 format have exponent fields of different length, depending on the size of the number. For faster computation, floating-point numbers are stored in floating-point registers in an internal form which corresponds to the format in which extended precision floating-point numbers are stored in memory: with a 15-bit exponent field, and without a hidden first bit in the significand.
As 128-bit extended floating-point numbers are already in this format in memory, all floating-point numbers will fit in a 128-bit register, although shorter floating-point numbers are expanded.
However, the 32 floating-point registers may also be used for Decimal Floating-Point (DFP) numbers. These numbers will also be expanded into an internal form for faster computation, but that internal form may take more than 128 bits.
This is dealt with as follows: Only 24 DFP numbers that are 128 bits in length may be stored in the 32 floating-point registers. When such a DFP number is stored in an even-numbered register, it is stored in that register, and the first 32 bits of the following register. When it is stored in a register the number of which is of the form 4n + 1 for integer n, the first 84 bits of the internal form of that number are stored in the last 84 bits of that register, and the remainder of the internal form of that number is stored in the last 84 bits of the second register after that register.
In this way, the same principle that storing double-length numbers in two adjacent registers is respected: numbers too long to be stored in a given register are stored in that register, and in another register of the same register file that is nearby. But the method is extended to allow more efficient use of the available space.
The same technique is used for the 128-bit floating-point format which has recently been added to IEEE 754 which does have a hidden first bit; therefore, in order to support this format, the usual 128-bit floating-point format offered by this architecture, while similar to, and based on, the Temporary Real format of the original 8087 coprocessor, has an exponent field that is one bit longer than that of the Temporary Real format.
There are 16 short vector registers, each of which is 256 bits in length.
Each of these registers may contain:
As well, they may contain sixteen 16-bit short floating-point numbers in one of two formats.
These numbers all remain in these registers in the same format as that in which they appear in memory.
The entire set of 16 short vector registers can contain a table of bits used for bit-matrix-multiply operations on 64 bit binary words. As well, the short vector registers may also be used as four string registers, each 128 bytes in length.
This is done, rather than using them as two string registers, each containing 256 bytes, because four registers are the minimum number of registers required for the general register style of operations, at least as claimed in advertising literature for the Data General Nova. Having these strings only half the maximum length of those available to memory-to-memory string operations is presumed to be accessible, since strings "really" only have to be at least 80 characters long, as everyone knows.
In addition to the basic set of registers, two other larger sets of registers are also included in the architecture:
A set of 128 64-bit integer registers, and a set of 128 128-bit floating point registers.
A set of 8 vector registers, each of which contains 64 storage locations for floating-point numbers, each one 80 bits wide. This allows the computer to process vectors of 72-bit floating-point numbers in addition to vectors of 64-bit floating-point numbers, if the optional variable memory width feature is included.
As for how data values are stored in memory:
Signed integer values are stored in binary two's complement format.
Floating-point numbers are stored in IEEE 754 format, but in addition there are instructions for processing data in the format originally used by IBM's System/360 computers, including the Extended Precision format introduced on the Model 85.
The architecture is big-endian: the most significant bits of a value are stored in the byte at the lowest numbered address.
As well, there are 16 flag bits which are used for instruction predication, and of course there is a 64-bit program counter. The program status quadword includes eight alternate sets of condition codes in addition to the normal set of condition codes, and the program counter and flag bits are also part of the program status quadword.
In general, as with most other computer architectures, instructions are provided to jump to a specified location in memory to continue execution.
In this architecture, instructions are considered to fall on 16-bit boundaries.
The normal rule for branch instructions is that their targets must be executable instructions. There are exceptions to that principle, as well as another special consideration, which apply to this architecture, however.
Athough these points might seem obvious, it should also be obvious that it is advisable to state them explicitly to avoid the possibility of confusion.