The formats of the basic 32-bit instructions for this architecture are shown in the three diagrams below:
First, the instructions that are 32 bits in length which can never affect the condition code bits, as they perform functions such as load and store, or jump, are shown.
The 32-bit form of basic load and store instructions is shown in lines 1 through 8.
For a memory-reference instruction, the five-bit destination register field specifies one of 32 registers, either the general-purpose registers for integer instructions, or the floating-point registers for floating-point instructions.
The index register field contains a number from 0 to 7, if it contains 0, the instruction is not indexed; if it contains any other value, that value indicates which general register is to be used as the index register for that instruction.
Lines 1 through 8 show the eight possible formats for 32-bit memory-reference instructions.
In line 1, a three-bit field indicates the base register. It may contain any value from 1 to 7, which indicates that a general register from 25 to 31 respectively is used as the base register.
Line 2 of the original diagram shows the second possibility: a 15-bit displacement is included in the instruction, and general register 16 contains the starting point of the 32,768-byte area of memory to which the values of this displacement may refer.
Line 3 of the original diagram shows the third possibility. Here, the displacement is 12 bits long, and there is a three-bit ssB field (short source base) adjacent to it.
If that field contains a number from 1 to 7, it indicates that a register from 17 to 23, respectively, is used as a base register, the contents of which point to a 4,096-byte area in memory.
If that field contains a 0, then one of the possibilities shown in lines 4 and 5 of the diagram apply.
Line 4 of the original diagram shows this possibility: if the ssB field, containing a 0, is followed by 00, then program-relative addressing is indicated.
The instruction now contains an 10-bit displacement, which is in units of bytes, but now it is a signed two's complement value from -512 to 511, relative to the position immediately after the end of the instruction. One particularly important application of this addressing mode is at the beginning of a main program or a subroutine, where a Jump to Subroutine instruction having the following instruction as its destination can be used to initialize a base register by means of which adresses referring to the program code can be constructed.
Lines 5 and 6 of the diagram are chiefly concerned with the register indirect addressing modes.
In line 5, we see where the ssB field, containing zero, is followed by 01, and the following mode field contains a value from 0 to 5, indicating an addressing mode used with one of the registers in the extended register bank.
These modes are:
000 Register Indirect 010 Register Indirect with Scaled Auto-Increment 011 Register Indirect with Scaled Auto-Decrement
In line 6, the ssB field again contains zero, and is followed by 0111 and then
a mode field. This field applies either to a register from the normal bank of
32 integer registers, or, in one case, the field normally specifying a register instead
contains a pseudo-immediate pointer. The modes are:
000 Register Indirect 010 Register Indirect with Scaled Auto-Increment 011 Register Indirect with Scaled Auto-Decrement 111 Absolute
In the absolute addressing mode, which may be indexed, the source register field instead contains a five-bit pseudo-immediate pointer which points to a 64-bit pseudo-immediate used as the address of the instruction.
For all load operations, auto-increment and auto-decrement are performed after the load operation; for all store operations, auto-increment and auto-decrement are performed before the store operation. In this way, it is possible for stacks to grow either up or down in memory, whereas, if whether an auto-increment or auto-decrement were performed had determined the ordering of operations, a specific direction of stack growth would be imposed.
Lines 7 and 8 of the diagram show the formats for two other addressing modes.
If the ssB field,
containing a 0, is followed by 100, then it indicates Array Mode addressing.
Here, the contents of register 16 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit pointer to an array.
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Unless the displacement begins with
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If indexing is present in the instruction, the contents of the selected register are added to that pointer in order to address an element of that array. Thus, Array Mode provides post-indexed indirect addressing in order to conveniently allow a program to refer to up to 512 arrays which are larger than 65,536 bytes in size without having to reload base registers in order to access them.
If the ssB field,
containing a 0, is followed by 101, then Address Table addressing is indicated.
Here, the contents of register 16 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit constant containing the effective address of the instruction.
If indexing is present in the instruction, the contents of the selected register are added to the initial effective address formed by adding the contents of register 17 to the displacement, so as to change which 64-bit constant is taken as the effective address.
Thus, Array Mode addressing provides pre-indexed indirection, and Address Table addressing provides post-indexed indirection. Array Mode addressing is useful for accesing data in multiple large arrays without reloading base registers, and Address Table addressing is useful for such things as multi-way jump tables.
If the ssB field, containing a 0, is followed by 110, then Array Mode with
Auto-Increment addressing is indicated. The displacement is in units of 64 bits, and
the contents of integer register 16 are added
to the displacement after scaling to find the address to be used; this address may be indexed to form
the effective address, and, in addition, after the memory location at the effective address so calculated
is accessed, the index register is then incremented by the size of the operands of the instruction;
incremented by one if the instruction acts on bytes, having eight added to it if the instruction acts
on double-precision floating-point numbers, and so on. This includes adding six in the case of medium
floating-point numbers.
If the ssB field, containing a 0, is followed by 111, then Array Mode with
Flexible Auto-Increment
addressing is indicated. Here, if the instruction is indexed, the index register must be one of
registers 2, 4, or 6, and the amount by which it is incremented after memory access is found in the
following register.
Line 9 of the diagram shows the format of the Load Address instruction. It has all the same addressing modes as the regular memory-reference load-store instructions shown in lines 1 through 8 of the diagram.
Lines 10, 11, and 12 of the diagram show the formats of the multiple-register load and store instructions:
0740xx xxxxx LM Load Multiple 0741xx xxxxx STM Store Multiple 0742xx xxx0x LMF Load Multiple Floating 0743xx xxx0x STMF Store Multiple Floating 0742xx xxx1x LMSV Load Multiple Short Vector 0743xx xxx1x STMSV Store Multiple Short Vector
Note that these instructions, in particular the ones for the floating-point registers, load and store their contents in raw internal form. Because of the complexities of the IEEE 754 format for floating-point numbers, they are converted to an internal form when loaded into the floating-point registers, and converted back to the standard form when stored from those registers, to allow register-to-register arithmetic to proceed more quickly.
As these instructions, with both a low and high register specified, require a considerable amount of opcode space, they have been restricted to aligned operands.
The Subroutine Jump instruction, depicted in line 13 of the diagram, has some important properties in this architecture that should be noted. Normally, the address of the location immediately following the instruction is stored in the return register field. But if the Subroutine Jump instruction is not in the last instruction slot of the current instruction block, but is still the last executable instruction in the block, the remaining part of the block being reserved, then the beginning of the next instruction block is used as the return address.
This avoids the need to fetch the next instruction block in order to scan it for its header, since a branch to the beginning of a block is always treated as a branch to the first executable instruction in a block.
Also, when a Subroutine Jump instruction is within a block where the starting positions of instructions are indicated for code with variable-length instructions, the actual position of the next executable instruction within the block as so indicated is used as the return address.
Note also that this instruction has a full three-bit base register specification and a full 16-bit displacement, which means that it may be used with the same selection of address modes as shown for the memory reference load/store instructions in lines 1 through 8 of the diagram. An important consequence of this is that the destination address may be in program-relative mode. This allows a Subroutine Jump instruction in this form to be used as the first instruction in a program, with the storage of the return address serving to initialize the first base register to be used. This is the same function as the BALR instruction was used for in the IBM System/360 computer.
Line 20 shows a special type of instruction which performs an important function when a special security feature is enabled. The Instruction field contains a 17-bit short instruction, as described on the next page. When controlled branching is enabled, all forms of jump instruction may only jump to an instruction of this type, which allows code to control its admissible entry points.
The diagram below shows the format for 32-bit instructions which perform arithmetic operations, and which may affect the condition codes:
Line 1 shows the format of single-operand register operations other than shifts; line 2 shows the format of shift instructions.
Line 3 shows a format for operate instructions with an immediate value eight bits in length that allows the immediate value to be included within the 32-bit instruction itself, instead of using additional space to place it outside the instruction.
Line 4 shows the Alternate Condition Code operate instructions; these instructions, instead of setting the normal condition codes, set one of eight alternative sets of condition codes. This helps to delay branches for better pipelined execution. Due to limitations of opcode space, these instructions may only use the first eight registers in each register bank as destination registers; a version without this restriction is in a set of alternative instructions.
Line 5 shows register-to-register operate instructions that involve extended register banks, both integer and floating, with 128 registers instead of 32 registers. Larger register banks permit more operations to be performed before there is a need to re-use a register from which the result has been stored, reducing the occurence of hazards in pipelined code.
The mixed register two-address instructions in line 6 allow the large register banks to interact with the normal register banks.
The formats for a three-address register-to-register operate instruction are shown in lines 7 through 9.
One, but not both, of the source and operand register specifications may be replaced by a pointer to a pseudo-immediate operand. This is a byte pointer within the current 256-bit instruction block. The bit combination indicating that both of these operands are replaced is reserved for future expansion.
Pseudo-immediate arguments are available in those blocks for which space for the immediate value may be reserved; this means those blocks with a header, whether that header is of Type I, Type II, or Type III.
In blocks with a Type I header, instructions may cross block boundaries. However, pseudo-immediate values may not cross block boundaries.
If either pImm field contains zero, however, it does not act as a pointer to a pseudo-immediate value. Instead, the instruction uses an immediate value which immediately follows the instruction. Since only the Type I header permits flexibility in indicating reserved locations within a block with arbitrary placement, normally this feature will only be used in blocks with a Type I header. (It could potentially be used with the last instruction in a block with a Type II or Type III header, positioned so that the immediate value would fall in the space reserved by the decode field, but this is not a recommended practice.) As an immediate value is an actual part of the instruction, it may cross the boundary, or be on the other side from the preceding portion of the instruction of the boundary, between two instruction blocks both of which have Type I headers.
Two-address register-to-register operate instructions are shown in lines 10 and 11. These have a larger space available for the opcode field, and, thus, are not restricted to the basic arithmetic operations provided for three operands. The source operand in these instructions may be an immediate or pseudo-immediate value, following the same rules as apply to three-operand instructions.
Line 12 shows the halfword immediate instructions.
The diagram below shows additional types of 32-bit instruction other than the basic memory-reference instructions; these instructions are available with restrictions on the operands they may use, or on indexing, or on their destination registers; less restrictive forms of these same instruction types are also available among the 48-bit instructions for use within a block with a Type I header.
Lines 1 through 18 show memory reference operate instructions.
In order to allow these instructions to fit in the available opcode space, they have a number of limitations.
Lines 19, 20, and 21 show the form of the Supplemental Load and Store operations. These instructions perform load and store operations from memory for operands of additional specialized types which are supported by some of the operate instructions with longer opcodes.
In order to allow these instructions to fit in the available opcode space, they have a number of limitations.