The Opcodes

Finally, although I won't attempt to completely specify the proposed example architecture, giving the opcodes of the various instructions, to show that it really is possible to fit the instructions for all the data formats intended to be supported in the space available would seem desirable.

Only the basic 18-bit register instructions and 36-bit memory-reference instructions are shown in full here, as these are the cases where opcode space is highly constrained.

00 SWBR  08 IBR   10 SWHR  18 IHR   20 SWR   28       30 IAHR  38  
01       09       11       19       21       29       31       39
02 LBR   0A ULBR  12 LHR   1A ULHR  22 LR    2A       32 LAHR  3A ULAHR 
03       0B XBR   13       1B XHR   23       2B XR    33       3B XAHR
04 ABR   0C NBR   14 AHR   1C NHR   24 AR    2C NR    34 AAHR  3C NAHR
05 SBR   0D OBR   15 SHR   1D OHR   25 SR    2D OR    35 SAHR  3D OAHR
06       0E       16 MHR   1E MEHR  26 MR    2E MER   36 MAHR  3E MEAHR 
07       0F       17 DHR   1F DEHR  27 DR    2F DER   37 DAHR  3F DEAHR

40 SWMR  48 SWFR  50 SWDR  58 SWAFR  60 SWADR  68 SWQR  70      78
41       49       51       59        61        69       71      79
42 LMR   4A LFR   52 LDR   5A LAFR   62 LADR   6A LQR   72 LAR  7A
43       4B       53       5B        63        6B       73      7B XAR
44 AMR   4C AFR   54 ADR   5C AAFR   64 AADR   6C AQR   74 AAR  7C NAR
45 SMR   4D SFR   55 SDR   5D SAFR   65 SADR   6D SQR   75 SAR  7D OAR
46 MMR   4E MFR   56 MDR   5E MAFR   66 MADR   6E MQR   76 MAR  7E MEAR
47 DMR   4F DFR   57 DDR   5F DAFR   67 DADR   6F DQR   77 DAR  7F DEAR

It has been necessary to omit, from 18-bit register-to-register instructions, the unnormalized operations on 144-bit extended precision floats, and to omit the 96-bit extended precision floats entirely, as well as excluding 72-bit integers, to fit into the available opcode space.

Thus, for the register-to-register operations, the mnemonics above follow the conventions used for the other architectures I have proposed; one can refer to this page to see the names spelled out in full.

The data type designations are:

36-bit memory

  B      Character (byte)         9 bits
  H      Halfword                18 bits
  (none) Word                    36 bits
  L      Doubleword (long)       72 bits

  F      Single (floating)       36 bits
  M      Intermediate (medium)   54 bits
  D      Double                  72 bits
  Q      Extended (quad)        144 bits

48-bit memory

 AH      Alternate Halfword      24 bits
 A       Alternate               48 bits

 AMS     Alternate Memory Single   36 bits
 AF      Alternate Floating        48 bits
 AD      Alternate Double          60 bits
 AMD     Alternate Memory Double   72 bits
 AE      Alternate Extended        96 bits

For the memory-reference instructions, the fact that only 64 opcodes are available is balanced by two considerations: only load and store instructions are provided in this form, and several opcodes refer to more than one instruction because the 36-bit memory-reference instructions operate only on aligned data, and thus the least significant bits of the displacement field are used to identify the data type.

Here, the opcodes are:

80 ULB         88 ULAH             90 LAMS
81 IB          89 IAH              91 STAMS
82 LB          8A LAH /LA          92 LAD
83 STB         8B STAH/STA         93 STAD
84 ULH         8C LM /LF /LD /LQ
85 IH          8D STM/STF/STD/STQ
86 LH /L /LL   8E LAMD /LAF /LAE

Thus, there not only are enough opcodes for these instructions, as well as twelve more positions among the first 32 of them for additional operations, such as loading and storing base register contents, jump, and subroutine jump, as well as the multiple register instructions and shift instructions, but in addition there is space for the vector register instructions; while they have four additional opcode bits, which will indicate the operation to be performed, one opcode is still needed within the first eight bits of the instruction for each data type used, so the space they require is not fully inconsequential.