Except for the most popular computer architecture, that which derives from the Intel 8086 microprocessor, the Motorola ColdFire series of chips, based on a simplified version of their discontinued 68000 architecture, and the chips IBM produces for its own zSystem mainframes, almost every microprocessor architecture in current production is of the Reduced Instruction Set Computing (RISC) type.
The RISC architecture contains several common elements. Some of them are no longer present in most chips that still call themselves RISC:
But most of the defining characteristics of RISC do remain in force:
Having every instruction occupy the same amount of space in memory greatly simplifies the design of the computer's control unit, the part which reads each instruction, and then guides the computer through the steps required to carry out the instruction.
Since loading an operand from memory requires the processor to wait for that operand to arrive, memory reference instructions that also perform arithmetic also complicate matters by requiring the computer, in effect, to schedule two activities arising from a single instruction.
Long before RISC became the norm, it was quite common for computers to have all instructions the same length. While some computers had instructions of varying length, such as the IBM 1401, the IBM 360, the PDP-11, and the 8086 and 68000 microprocessors, the IBM 7090, the SDS Sigma, and the Control Data 1604 computers all had only one size of instruction.
The following diagram illustrates the instruction formats of a hypothetical computer which attempts to provide facilities only found on computers with complex rather than reduced instruction sets, still takes some inspiration from RISC designs:
Seventeen possible instruction formats are shown.
The first eleven formats are the ones used for instructions that reference memory. The opcode space used by these instructions is reduced by having them always refer to aligned operands, and using the unused less-significant positions of the address to help to indicate the operand type. Conditional jump and subroutine jump instructions are also placed in this area.
The twelfth instruction format is used for string and packed decimal operations, as well as pipelined vector arithmetic. Since these are memory-to-memory operations with two addresses, a set of eight pointer registers is used to supply the addresses.
The thirteenth instruction format is used to permit string and packed decimal operations to be set up with only one load address instruction. In order to achieve this, it has some limitations. An instruction using the second instruction format must have been previously executed, and the first six bits of that instruction's opcode, which are saved in the status register, are combined with the three bits of the opcode for this instruction (which may not all be zero) to form the opcode. As well, only pointer register zero may be used as the destination pointer register, and its contents cannot be indexed.
The fourteenth instruction format contains two register-to-register instructions. It has the restriction that both of these instructions must be able to execute simultaneously, thus they must use different arithmetic units.
The fifteenth instruction format combines one register-to-register instruction with a shift instruction.
The sixteenth instruction format contains three register-to-register instructions which must be able to execute in parallel. The first instruction is an integer instruction, which is applied to the most recent integer type specified, and the second is a floating-point instruction, which is applied to the most recent floating-point type specified; both of these types are retained in the status register. The third instruction is any one that can be executed in parallel with the preceding two instructions. The first two instructions can only have registers 0 and 1 as their destination registers; as a result, the store instruction as well as the load instruction is valid for them even though they are register to register instructions.
The seventeenth instruction format performs integer or floating-point single operand instructions (the interpretation of the type field depends on the instruction being performed) combined with two register-to-register instructions, the first being of the most recent integer type, the second being of the most recent floating-point type specified.
The complement of registers associated with this architecture is the following:
In addition, there is a program counter, and a status word.
Some other architectures using RISC concepts will be dealt with in later pages of this section.